AMD CEO talks of long-term turnaround

[NTMBK]

There is one custom add-on to Jaguar in the XB1 APU and that is a custom connection to the ESRAM from the Jaguar CPU. It could support VISC like functionality and it's similar to what Zen is getting with a large ESRAM cache in addition to DDR4.

Sorry Jeff, I don't quite follow- how does ESRAM enable a VISC architecture? VISC requires a CMT-style unified front end across multiple cores, so that it can issue instructions to them all and treat them like a single core if required. The ESRAM is just a high speed scratchpad.

Nintendo NX is likely to have the same and that could allow it to emulate the Power PC in the WiiU. Since the XB1 is doing this for Xbox 360 BC on the XB1, I think that sorta indicates it's possible. The only speculation is that the custom Jaguar to ESRAM is needed.

I do wonder if the possibility of backwards compatibility is why Microsoft went with their ESRAM design- it seems like a clever move, to sort-of-replicate the EDRAM setup from the 360.

I'm not convinced that NX will be backwards compatible with the Wii U, though- the main issue is the Wii U controller. You would need a handheld touchscreen controller, and this is the major factor which pushed up Wii U price and also made it tricky to develop for. (Even Nintendo games like Donkey Kong have completely ignored it!) Including that expensive feature just to provide backwards compatibility with a deeply unpopular console seems like a poor decision.

Of course, they could perhaps do it by letting you use the "NX handheld" as a controller for the "NX console", similar to the Gamecube-GBA connection:

But like the Gamecube-GBA connection, I would expect it to be an optional extra which is used in a handful of games (and backwards compatibility), instead of being a bundled accessory.

 

[Dresdenboy]

you have to check the link by yourself
http://vcew.org/CE-Vail-2014-Program.pdf

so Jeff can post a patent, but no proof ?
but that actual keynote is a fake ? LOL

from Trinity Designer & John Sell not a proof?
check the link
"Xbox One Next gen Processor"
that is not fake !!!


we are educated guys here
all is linked to real link

Linkedin is real, just searh Kryptos HP-APU in linkedin

also unless Jaguar suddenly categorized as HP-APU
good debate is when we are debating from real source then assumption based on that

The links are real, but this doesn't validate wrong conclusions. And there is room of interpretation in any human language. The XB1 APU has much higher BW, core count, avg. CPU MT and GPU performance than any APU sold by AMD itself. So if you don't accept this due to the Jaguar cores, you should rethink it.

And there is one more thing: Sebastien Nussbaum was involved in many low power techs and optimizations and helds many related patents. Since Trinity is a mobile APU, this would also make sense to have one with that experience to oversee things there. But I didn't read "Chief Architect". So what's his real role there? He had never much to do with core logic btw.

 

[Dresdenboy]

I'm not convinced that NX will be backwards compatible with the Wii U, though- the main issue is the Wii U controller. You would need a handheld touchscreen controller, and this is the major factor which pushed up Wii U price and also made it tricky to develop for. (Even Nintendo games like Donkey Kong have completely ignored it!) Including that expensive feature just to provide backwards compatibility with a deeply unpopular console seems like a poor decision.

Agreed. I think, the Wii U was the product of some dreams about socializing the families again. But most players, even with MP games, play and stream alone. And other family members have their own interests, duties, or other time consumers. In the end they had to do something revolutionary. And maybe they even listened to Chris Crawford. But it didn't match reality. One thing might work better here: Microsoft's Holo Lens (at least as an addon).

 

[Dresdenboy]

There is one custom add-on to Jaguar in the XB1 APU and that is a custom connection to the ESRAM from the Jaguar CPU. It could support VISC like functionality and it's similar to what Zen is getting with a large ESRAM cache in addition to DDR4.

Nintendo NX is likely to have the same and that could allow it to emulate the Power PC in the WiiU. Since the XB1 is doing this for Xbox 360 BC on the XB1, I think that sorta indicates it's possible. The only speculation is that the custom Jaguar to ESRAM is needed.

Did you mean more the like of in-memory computing? AMD is working on that. So far it covers only simple tasks. VISC is a whole new arch and ISA. The patents tell a lot about it:
http://www.freepatentsonline.com/re...&query_txt=(an/"Soft+Machines")&search=Search

So far the protoype has been estimated to run at 350 MHz. Still far from being a contender.

Sony and Microsoft took SOME AMD 2016 features and implemented them in 2013 Game Consoles, nothing more. It's not a super APU, nothing like what's coming in 2016 when everything planned is implemented.

Sure it's likely "Xbox One Next gen Processor" means Microsoft took a expensive AMD 2016 feature and implemented it... giving them the ability to support a 2016 feature called VISC which increases single thread IPC with multiple CPUs and as a side benefit allows X-86 CPUs to emulate RISC processors (ARM and Power PC) . This is a must have feature when AMD implements efficiencies in that many slower CPUs are more efficient than a few higher clocked CPUs. AMD's Zen must support VISC! The Zen CPUs will be smaller slower clocked (with turbo and power scaling). The Jaguar 4 CPU to a package is the same as Zen but with ZEN blocks of 8 will likely be the rule with multiples, 8 or 16 CPUs probably due to embedded on chip power supplies designed for 8 CPU blocks.

VISC designs feature 4 virtual CPUs and require a minimum number of real world CPUs for the most efficiency. MisterCteam was posting Microsoft studies on SemiAccurate about 4 CPU packages which I think applies to this.

What did Microsoft implement on its own in the APU? I think it's more like they negotiated SoC requirements with AMD and provided some IP blocks, while AMD is implementing it (with some help of MS engineers).

VISC is not a feature, is a whole new architecture, replacing the old stuff. It's a mix of a reconfigurable uarch and Transmeta like translation. Intel and AMD are already going the route of bringing adaptivity to the processor's units to be more power efficient or to share it more effciently.

VISC requires a lot of flexible communication between the physical hardware units, more like in a GPU and its register files, etc. We know the usual operating clock frequencies of GPUs. Wire delays are not "free" anymore. And flexibility has its own costs.

Even the proposed MorphCore paper is likely off by a factor of 5 regarding the clock impact of the additional path and the related multiplexers.

Let's first see, how VISC turns out to be before assuming it's final implementation in Zen or XB1 many years before its maturity.

 

[NTMBK]

What did Microsoft implement on its own in the APU? I think it's more like they negotiated SoC requirements with AMD and provided some IP blocks, while AMD is implementing it (with some help of MS engineers).

Didn't Microsoft contribute some of the IP blocks to do with Kinect processing? Audio/video decode/analysis, something along those lines, I forget the details.

 

[jeff_rigby]

Didn't Microsoft contribute some of the IP blocks to do with Kinect processing? Audio/video decode/analysis, something along those lines, I forget the details.

Microsoft designed their own Xtensa DPU using Cadence-Tensilica-Xtensa configurable IP. Same with Sony in the PS4 Southbridge and AMD has been doing since the first APU.

 

[jeff_rigby]

Did you mean more the like of in-memory computing? AMD is working on that. So far it covers only simple tasks. VISC is a whole new arch and ISA. The patents tell a lot about it:
http://www.freepatentsonline.com/re...&query_txt=(an/"Soft+Machines")&search=Search

So far the protoype has been estimated to run at 350 MHz. Still far from being a contender.

What did Microsoft implement on its own in the APU? I think it's more like they negotiated SoC requirements with AMD and provided some IP blocks, while AMD is implementing it (with some help of MS engineers).

VISC is not a feature, is a whole new architecture, replacing the old stuff. It's a mix of a reconfigurable uarch and Transmeta like translation. Intel and AMD are already going the route of bringing adaptivity to the processor's units to be more power efficient or to share it more effciently.

VISC requires a lot of flexible communication between the physical hardware units, more like in a GPU and its register files, etc. We know the usual operating clock frequencies of GPUs. Wire delays are not "free" anymore. And flexibility has its own costs.

Even the proposed MorphCore paper is likely off by a factor of 5 regarding the clock impact of the additional path and the related multiplexers.

Let's first see, how VISC turns out to be before assuming it's final implementation in Zen or XB1 many years before its maturity.

350 Mhz is the optimum clock speed using current Silicon and that is why 350 Mhz was chosen. It's not that a Visc CPU has to run at that speed. Xtensa processors also optimally run at 350 Mhz according to Cadence. Visc can run on any CPU IP, it's not tied to a custom CPU which is why Samsung, AMD and Globalfoundries invested in the research. From my limited understanding, it would need a very fast and relatively large cache which would be the ESRAM and the custom Jaguar to ESRAM modification in the XB1 APU. And we don't know what the custom Jaguar CPU package to ESRAM included.

The VISC research project designed a CPU with the optimum features and used that to test against current CPUs. This does not preclude AMD and Samsung/ARM from using VISC features with minor changes to the microcode and hardware in their CPUs. Global Foundries might try to sell the VISC CPU design to both Samsung and AMD as it can emulate any CPU IP. There are may ways this can go.

In any case I said Visc like which would have similar memory and CPU needs. That multiple 1.6 Ghz Jaguar X-86 cpus are emulating 2 Xbox 360 Power PC CPUs @ 3.2 Ghz (one CPU is doing audio and other OS features that are API served and can be replaced by dedicated hardware) would at times, on select code, have a IPC MUCH higher than a 1.6 Ghz CPU can emulate so it must be VISC like.

In the near future with 8-16 cpus replacing 2-4 more powerful "desktop" cpus, VISC or something like it is an essential must have.

 

[Dresdenboy]

350 Mhz is the optimum clock speed using current Silicon and that is why 350 Mhz was chosen. It's not that a Visc CPU has to run at that speed. Xtensa processors also optimally run at 350 Mhz according to Cadence. Visc can run on any CPU IP, it's not tied to a custom CPU which is why Samsung, AMD and Globalfoundries invested in the research. From my limited understanding, it would need a very fast and relatively large cache which would be the ESRAM and the custom Jaguar to ESRAM modification in the XB1 APU. And we don't know what the custom Jaguar CPU package to ESRAM included.

For now it is possible to create different ISA translations for that hardware. They're currently supporting the easier to handle ARM ISA.

What I meant is that adding this technology to existing cores means a lot of rework, as those are optimized to the max. And any little physical distance between the VISC cores will create delays, making the whole thing slower. The only more advanced architectures (no Tilera etc.) being close to what's needed are the Bulldozer family and maybe Cell. Look at their core diagram:
http://softmachines.com/wp-content/uploads/2015/01/MPR-11303.pdf

Also Jim Kellers project (with Dave Christie) comes to my mind, the K8-1:
http://chip-architect.com/news/2001_10_02_Hammer_microarchitecture.html
With that the "reverse hyperthreading" patent:
http://patft.uspto.gov/netacgi/nph-...50&s1=6574725.PN.&OS=PN/6574725&RS=PN/6574725
And others.

Speculative Multithreading is another one, as Anaphase. None of them hit the market.

The VISC research project designed a CPU with the optimum features and used that to test against current CPUs. This does not preclude AMD and Samsung/ARM from using VISC features with minor changes to the microcode and hardware in their CPUs. Global Foundries might try to sell the VISC CPU design to both Samsung and AMD as it can emulate any CPU IP. There are may ways this can go.

You know, that for such tech to be included at the high uarch level, it would have had to be ready in 2012 to get into Zen. We've seen the demo last year.

For such fundamental concepts there is a lot of integration work needed. Add to that the heavily increasing testing and validation efforts, new software, etc. We're not talking 8 bit non pipelined processors here. For any background I suggest the David Patterson books.

In any case I said Visc like which would have similar memory and CPU needs. That multiple 1.6 Ghz Jaguar X-86 cpus are emulating 2 Xbox 360 Power PC CPUs @ 3.2 Ghz (one CPU is doing audio and other OS features that are API served and can be replaced by dedicated hardware) would at times, on select code, have a IPC MUCH higher than a 1.6 Ghz CPU can emulate so it must be VISC like.

In the near future with 8-16 cpus replacing 2-4 more powerful "desktop" cpus, VISC or something like it is an essential must have.

The PowerPC cores are a long pipelined (21 stages) 2-wide in-order design with SMT. Except for the beefed up vector units, they're no performance monsters despite the misleading clock frequency. Here is some algo (I think, it was some clothing simulation) implemented on different console chips:

Adding VISC for some XBox 360 emulation would also too late as for Zen. For now any of the max. 6 PPC threads could run on a single Jaguar core. I think one problem is the number of architectural integer and FP + SIMD registers. PPC has 32 each IIRC, while Jaguar has 16 int and 16 FP/SIMD (not separated). Having to spill that to cache is horror. Then the PPCs have separate condition regs and other features, which couldn't even be mapped that easily using VISC.

 

[jeff_rigby]

For now it is possible to create different ISA translations for that hardware. They're currently supporting the easier to handle ARM ISA.

What I meant is that adding this technology to existing cores means a lot of rework, as those are optimized to the max. And any little physical distance between the VISC cores will create delays, making the whole thing slower. The only more advanced architectures (no Tilera etc.) being close to what's needed are the Bulldozer family and maybe Cell. Look at their core diagram:
http://softmachines.com/wp-content/uploads/2015/01/MPR-11303.pdf

Also Jim Kellers project (with Dave Christie) comes to my mind, the K8-1:
http://chip-architect.com/news/2001_10_02_Hammer_microarchitecture.html
With that the "reverse hyperthreading" patent:
http://patft.uspto.gov/netacgi/nph-...50&s1=6574725.PN.&OS=PN/6574725&RS=PN/6574725
And others.

Speculative Multithreading is another one, as Anaphase. None of them hit the market.


You know, that for such tech to be included at the high uarch level, it would have had to be ready in 2012 to get into Zen. We've seen the demo last year.

For such fundamental concepts there is a lot of integration work needed. Add to that the heavily increasing testing and validation efforts, new software, etc. We're not talking 8 bit non pipelined processors here. For any background I suggest the David Patterson books.


The PowerPC cores are a long pipelined (21 stages) 2-wide in-order design with SMT. Except for the beefed up vector units, they're no performance monsters despite the misleading clock frequency. Here is some algo (I think, it was some clothing simulation) implemented on different console chips:

Adding VISC for some XBox 360 emulation would also too late as for Zen. For now any of the max. 6 PPC threads could run on a single Jaguar core. I think one problem is the number of architectural integer and FP + SIMD registers. PPC has 32 each IIRC, while Jaguar has 16 int and 16 FP/SIMD (not separated). Having to spill that to cache is horror. Then the PPCs have separate condition regs and other features, which couldn't even be mapped that easily using VISC.

From your cite is this

Soft Machines hopes to license the VISC technology to other CPU-design companies, which could add it to their existing CPU cores

Some of this is just software, some optimizations are hardware of course. If the VISC CPU is a simpler design as stated then the hardware parts should be easy to implement. In the cite it mentions that both VISC and standard CPU functions are needed, at least for the near future. So the idea is to have X-86 CPUs that can run VISC code.

I don't disagree with most of your post just that you may be looking at this backwards. VISC is needed for Zen and since AMD knew this they already included VISC optimizations not that they have to start designing in VISC after the Visc paper is made public (2014).

If AMD has Jaguar cores and Zen cores and stated publicly that many slower clocked CPUs are better than a few monster higher clocked CPUs they knew something like VISC was needed. They invested in VISC starting in 2008 and likely feedback from VISC impacted their designs for Jaguar and Zen.

Soft Machines is no fly-by-night operation. The company
has spent seven years and $125 million to develop
and validate its technology. It currently has more than
250 employees, led by CEO Mahesh Lingareddy and
president/CTO Mohammad Abdallah. Investors include
AMD, GlobalFoundries, and Samsung as well as government
investment funds from Abu Dhabi (Mubdala), Russia
(Rusnano and RVC), and Saudi Arabia (KACST and
Taqnia). Its board of directors is chaired by Global Foundries
CEO Sanjay Jha and includes legendary entrepreneur
Gordon Campbell.

Assuming the technology works as advertised, it will
change the way all processors are designed. CPU designers
will stop trying to improve IPC by adding more hardware;
in fact, complex high-IPC designs like Haswell could disappear
in favor of smaller, simpler ones. Replacing large
cores with clusters of simpler cores will improve performance
and power efficiency, benefiting almost every type
of processor. To deliver on this promise, Soft Machines
must fully validate VISC and license it to leading processor
vendors. ♦

Aren't Jaguar and Zen designs following the above?

 

[Dresdenboy]

From your cite is this

Some of this is just software, some optimizations are hardware of course. If the VISC CPU is a simpler design as stated then the hardware parts should be easy to implement. In the cite it mentions that both VISC and standard CPU functions are needed, at least for the near future. So the idea is to have X-86 CPUs that can run VISC code.

BTW, here is a yesteryear's thread already discussing the stuff incl. many points similar to mine: http://forums.anandtech.com/showthread.php?t=2405469

What's missing there is the look at the available patents, which should answer many question, which came up in the thread.

But to your statement: Softmachines build a less complex, shallow pipelined prototype core uarch from scratch. Everything needed for VISC has been baked in from the beginning. And since this is a less complex uarch, this also didn't bring up too many problems due to complexity, critical timing etc. If VISC enters at this state, everything is fine. But if you look into the patents, you'll already see a lot of complex stuff there, which are needed for VISC (ISA translations, ALU mappings, schedulers, flag handling, registerfile mappings etc.).

With this description of VISC and the low clockspeeds, they of course didn't see many timing problems yet. But the faster they get, the more cycles will be added here and there, making the whole thing less efficient. This has to be sorted out to be no drag.

Interesting quote from the MPR article:

"Soft Machines has run many tests and simulations of its VISC technology. It estimates the second core improves performance by an average of 50–60% across a variety of benchmarks. This factor implies that the test chip would achieve about 1.3 IPC when using a single core—consider- ably higher than Cortex-A15. This higher IPC includes the effects of the lower clock speed and shorter pipeline"

I can even imagine a VISC processor running ARM and x86 code as needed. AMD might already think about that. But adding it to a design like Zen ("build from scratch" and "reusing existing building blocks") is a huge task. I work on collision avoidance ADAS, where there already are hundreds to thousands of signals. Even small changes cause a lot of work from specification updates through to the system tests over many levels.

I don't disagree with most of your post just that you may be looking at this backwards. VISC is needed for Zen and since AMD knew this they already included VISC optimizations not that they have to start designing in VISC after the Visc paper is made public (2014).

By this logic, AMD would have made a Bulldozer with much higher single thread performance.

Many significant VISC patents have been filed in 2012 and later. Softmachines surely had to work on the concept first, create simulators and so on before getting that far. It's not like they improved a MIPS core. And with such radical changes I'd expect at least some collaboration starting with the design phase.

Current cores are that fast and highly clockable due to a lot of techniques and tuning. If they take them apart to add VISC, they'd first end up with some fast individual execution units and lots of units, which have to be reworked. This means going away from the current optimal design points and finding new ones.

Of course the topic sparked my interest, but I won't expect it to hit the market before 2018.

If AMD has Jaguar cores and Zen cores and stated publicly that many slower clocked CPUs are better than a few monster higher clocked CPUs they knew something like VISC was needed. They invested in VISC starting in 2008 and likely feedback from VISC impacted their designs for Jaguar and Zen.

They said that since the X2, and other firms or research groups already went much further back then. Chuck R. Moore always proposed the coming of increasingly multithreaded software and parallelization per se (as far as HSA goes). It's not like most SW couldn't be parallelized. But assuming this leads to a strategy which forces more cores and heterogeneous computing. Besides slowing down the clock frequency race, Intel still continued to increase single threaded performance each year. This plus complex existing software plus human factors, budgets etc. seem to have put a slight brake on any efforts in this regard. This is just my impression.

Aren't Jaguar and Zen designs following the above?

Yes, they are. And on consoles it's easier to get the developers adapt to it given the fixed (and even similar) HW. Btw, SMT is proven and simpler to implement. And there are many people out there with experience developing that.

 

[buletaja]

The links are real, but this doesn't validate wrong conclusions. And there is room of interpretation in any human language. The XB1 APU has much higher BW, core count, avg. CPU MT and GPU performance than any APU sold by AMD itself. So if you don't accept this due to the Jaguar cores, you should rethink it.

And there is one more thing: Sebastien Nussbaum was involved in many low power techs and optimizations and helds many related patents. Since Trinity is a mobile APU, this would also make sense to have one with that experience to oversee things there. But I didn't read "Chief Architect". So what's his real role there? He had never much to do with core logic btw.

trinity is mobile APU but not low performance
with your track record u sure know about it

AMD listed HP-APU as datacenter oriented
trinity is part of it

Liano is low performance one
then succeeded with Jaguar etc

also u should know that AMD PIM is designed using trinity as based
AMD PIM use per CU group 12CU (basically like 2 module of trinity)

 

[buletaja]

i will posted this
just to open your mind

this is from XBOX director SOC patent

before reading this i sugest you check X1 XDK
then also check the XDK about move engine block is send vertices and command to gfx core, of course no one try to decrypt those hint.

there is many big hint in XDK
like:
1. X1 support 16 VA page (by GPUMMU), PS4 or GCN only support IOMMU = 1 VA
2. X1 has TLB on L1 (mimic Kepler) (thats why GPUMMU is possible)
3. X1 support 48 TCP, on other page TCP is per CU, then u can guess why they
make the diagram on hotchip like that, because each block is CUs
just like X1 director SOC patent

the patent : Software pipelining (make GPU to be like a CPU, a fully programmable GPU)
the patent diagram showed a raster based rendering pipeline configuration
but can be change into any custom pipeline: ray tracing, hybrid rendering etc

the patent: http://i.imgur.com/cUshqr9.jpg
each IPblock in patent described as can be: SIMD from GPU, DSP or etc
but each PE block is connected in NOC fashion

 

[buletaja]

Oh BTW AMD Fast forward (processing in memory) PIM architect has Patent for Microsoft for multi ISA
one of PIM Architect is Mike Ignatowski

PIM also clocked low (like my speculative of esram Speed)
PIM also sized in same size as current HBM which is also same as eSRAM
which is 35-40mm2

also sure with many clever people here
people should also questioning Chipwork
why Samsung or even TSMC HDL (High density library of 6T SRAM) of 16nm FF or 20nm could not even match eSRAM 16MB in area of 35-40nm2 ?
that if we believe what chipwork said esram is 28nm

 

[jeff_rigby]

BTW, here is a yesteryear's thread already discussing the stuff incl. many points similar to mine: http://forums.anandtech.com/showthread.php?t=2405469

What's missing there is the look at the available patents, which should answer many question, which came up in the thread.

But to your statement: Softmachines build a less complex, shallow pipelined prototype core uarch from scratch. Everything needed for VISC has been baked in from the beginning. And since this is a less complex uarch, this also didn't bring up too many problems due to complexity, critical timing etc. If VISC enters at this state, everything is fine. But if you look into the patents, you'll already see a lot of complex stuff there, which are needed for VISC (ISA translations, ALU mappings, schedulers, flag handling, registerfile mappings etc.).

With this description of VISC and the low clockspeeds, they of course didn't see many timing problems yet. But the faster they get, the more cycles will be added here and there, making the whole thing less efficient. This has to be sorted out to be no drag.

Interesting quote from the MPR article:


I can even imagine a VISC processor running ARM and x86 code as needed. AMD might already think about that. But adding it to a design like Zen ("build from scratch" and "reusing existing building blocks") is a huge task. I work on collision avoidance ADAS, where there already are hundreds to thousands of signals. Even small changes cause a lot of work from specification updates through to the system tests over many levels.


By this logic, AMD would have made a Bulldozer with much higher single thread performance.

Many significant VISC patents have been filed in 2012 and later. Softmachines surely had to work on the concept first, create simulators and so on before getting that far. It's not like they improved a MIPS core. And with such radical changes I'd expect at least some collaboration starting with the design phase.

Current cores are that fast and highly clockable due to a lot of techniques and tuning. If they take them apart to add VISC, they'd first end up with some fast individual execution units and lots of units, which have to be reworked. This means going away from the current optimal design points and finding new ones.

Of course the topic sparked my interest, but I won't expect it to hit the market before 2018.


They said that since the X2, and other firms or research groups already went much further back then. Chuck R. Moore always proposed the coming of increasingly multithreaded software and parallelization per se (as far as HSA goes). It's not like most SW couldn't be parallelized. But assuming this leads to a strategy which forces more cores and heterogeneous computing. Besides slowing down the clock frequency race, Intel still continued to increase single threaded performance each year. This plus complex existing software plus human factors, budgets etc. seem to have put a slight brake on any efforts in this regard. This is just my impression.


Yes, they are. And on consoles it's easier to get the developers adapt to it given the fixed (and even similar) HW. Btw, SMT is proven and simpler to implement. And there are many people out there with experience developing that.

You mentioned and in the cite it mentions that there is a memory bottleneck with multiple CPUs and increasing the CPU clock speed using VISC. VISC then likely wasn't practical without larger more EXPENSIVE cache. "As an example the workload in question runs at 5.4 on a 6 issue wide within L2. 4.5 at L3 and drops to a stagnating 0.8 when going to main memory." The first AMD APU to have a Jaguar to large ESRAM connection is the XB1. Zen departs from Jaguar in the way it handles instructions, more like Intel cpus which is needed for a more efficient VISC. From my limited understanding, the patents I read are mostly software routines which can be handled by a CPU. The converting of a X-86 instruction to many smaller CPU instructions that are then scheduled by virtual CPUs requires larger faster cache and sharing L2 between at least two processors...which is what Jaguar does. The VISC design in the cite reminds me of some of the Jaguar features.

Anyway that's my impression for what it's worth, I am not a professional and don't have a finer understanding of the details.

QUOTE = http://forums.anandtech.com/showpost.php?p=36842270&postcount=18

 

[jeff_rigby]

Oh BTW AMD Fast forward (processing in memory) PIM architect has Patent for Microsoft for multi ISA
one of PIM Architect is Mike Ignatowski

PIM also clocked low (like my speculative of esram Speed)
PIM also sized in same size as current HBM which is also same as eSRAM
which is 35-40mm2

also sure with many clever people here
people should also questioning Chipwork
why Samsung or even TSMC HDL (High density library of 6T SRAM) of 16nm FF or 20nm could not even match eSRAM 16MB in area of 35-40nm2 ?
that if we believe what chipwork said esram is 28nm

This is MisterCteam right? You bring up interesting information but PIM is clocked low because RAM can't handle heat. The next generation memory is likely Resistive and does not suffer from heat as much as the current version. PIM won't likely be practical till resistive memory is main stream.

Stacked or PIM Memory size is limited by the weakest link which is the TSV pitch. That they are similar in size to the ESRAM in XB1 at 28nm might be by design as you allude. The packaging machinery for 3D and 2.5D has likely been created to work with standards that every design is trying to adhere to.

RE: The XB1 APU and 4 move controllers. I looked into that early 2013 when that was leaked and posted about Cadence using 4 Memory controllers for ARM designs. Turns out the Memory controllers, in fact just about everything in the AMD APU except Jaguar and the GCN GPU is Cadence IP on an ARM bus.

Microsoft working with Cadence tools created a custom ARM block for the XB1 just as AMD does with Cadence for it's APUs. As Cadence produces more powerful elements, Xtensa IVP for instance, AMD incorporates them in it's APUs. Xtensa IVP blocks have move controllers. Do some research on Xtensa processors or start with these cites.

http://www.neogaf.com/forum/showthread.php?t=916219
http://www.neogaf.com/forum/showpost.php?p=166541391&postcount=368

 

[Dresdenboy]

You mentioned and in the cite it mentions that there is a memory bottleneck with multiple CPUs and increasing the CPU clock speed using VISC. VISC then likely wasn't practical without larger more EXPENSIVE cache. "As an example the workload in question runs at 5.4 on a 6 issue wide within L2. 4.5 at L3 and drops to a stagnating 0.8 when going to main memory." The first AMD APU to have a Jaguar to large ESRAM connection is the XB1. Zen departs from Jaguar in the way it handles instructions, more like Intel cpus which is needed for a more efficient VISC. From my limited understanding, the patents I read are mostly software routines which can be handled by a CPU. The converting of a X-86 instruction to many smaller CPU instructions that are then scheduled by virtual CPUs requires larger faster cache and sharing L2 between at least two processors...which is what Jaguar does. The VISC design in the cite reminds me of some of the Jaguar features.

Anyway that's my impression for what it's worth, I am not a professional and don't have a finer understanding of the details.

QUOTE = http://forums.anandtech.com/showpost.php?p=36842270&postcount=18

The memory "wall" is a typical effect of high frequency designs. Also a narrow memory bus might limit IPC. This is where high Dhrystone, Coremark and similar benchmarks don't match reality due to a 32b memory bus.

The quoted example was for Itanium family CPUs. Depending on the possibility to apply efficient cache blocking the large mem footprint IPC doesn't need to drop off that much.

Is the Jaguar ESRAM cache coherent memory? If not, we can stop discussing it here.

The Softmachines patents also describe a lot of hardware units and how they handle the many different threadlets with their own execution environments each, and so on. There's also hardware to improve the ISA translation.

Looking at the Zen uarch at this point in time is like looking into a fog with 5m sight. I can't tell if there is VISC, Hardware Lock Elision, or a Chinese Dragon.

The shallow VISC pipeline doesn't mean, that they had supersimple native instructions. And splitting x86 ops into too many uops just creates too much overhead. In fact most x86 ops incl. those with simple memory adressing modes are translated to 1 ALU uop and 1 AGU op in Intel and AMD processors. Both can be handled as a fused op (done since K7).

 

[buletaja]

@Jeff of course PIM has to be low it is clocked same as eSRAM clocked
you know why Charlie hinted low clock 426Mhz for long
i know charlie dont like MS so do most people at S|A (i dont know why)
but his hint are correct

first PIM is designed to be multi stacked
the CPU has to be under SRAM or DDR dies because CPU is clocked bit higher (produce more heat) than Vector (GPU part), the GPU is clocked LOW

you know why PIM is per 6 CU or 12CU
because it is use Trinity as a based

 

[buletaja]

Just for fun this is Mike Ignatowski patent from IBM then Microsoft --> MULTI ISA (PPC/X86 etc)

then this is when AMD CTO congratulate Mike for success of AMD PIM (Fast Forward prj)
https://community.amd.com/community...res-third-consecutive-exascale-research-grant

You wll find Mike patent in various patent
also in Wafer to wafer (non silicon interposer) or called as active interposer

 

[ocre]

The memory "wall" is a typical effect of high frequency designs. Also a narrow memory bus might limit IPC. This is where high Dhrystone, Coremark and similar benchmarks don't match reality due to a 32b memory bus.

The quoted example was for Itanium family CPUs. Depending on the possibility to apply efficient cache blocking the large mem footprint IPC doesn't need to drop off that much.

Is the Jaguar ESRAM cache coherent memory? If not, we can stop discussing it here.

The Softmachines patents also describe a lot of hardware units and how they handle the many different threadlets with their own execution environments each, and so on. There's also hardware to improve the ISA translation.

Looking at the Zen uarch at this point in time is like looking into a fog with 5m sight. I can't tell if there is VISC, Hardware Lock Elision, or a Chinese Dragon.

The shallow VISC pipeline doesn't mean, that they had supersimple native instructions. And splitting x86 ops into too many uops just creates too much overhead. In fact most x86 ops incl. those with simple memory adressing modes are translated to 1 ALU uop and 1 AGU op in Intel and AMD processors. Both can be handled as a fused op (done since K7).

Yep, the hardware has to be there. I am having a having a hard time with this, you cant have magic SW that can run anything without penalty. The idea of VISC makes sense and perhaps it is viable, but it only makes sense to me with specific and radically different HW. "some of it is HW", I just find it completely impossible without huge penalties in speed and capability.

I am not buying some Esram and Jaguar + software can magically transform into a VISC powerhouse.

How can we talk about Xbox One Esram like this? Are their people that dont realize the massive bandwidth discrepancy between the PS4 and Xbone? M$ opted for a cheap and slow 8gb of DDR3 while Sony wisely chose Gddr5. No need to make up other reasons, M$ needed a buffer. Just think about it, without esdram, the entire system is at the mercy of the slow ddr3 system ram. The Esram is 3 times faster than the rest of the ddr3 on the system and similar to the speed of the Gddr5 on the Ps4.

The xbox 360 also has Esram, perhaps this was also a VISC future looking design..... Or maybe the inclusion of Esram in the XB360 helped influence the Esdram in the Xbox one. Their engineers already had experience with such a setup and perhaps parts of their GUI/OS/kinnect/etc functionality was built to take advantage of having a fast and high bandwidth segment of memory. M$ may have planned on trying to emulate the 360 for backwards capability, this could have played a role as well.

To me, I dont see a lot of point in thinking of alternate theories of why the Esram is in the xbox one. It doesnt point to some secret capability that will be unlocked one day. I think the xbox without esram would have a much harder time than it does today trying to keep up with the PS4. No need for more far fetched reasons.

 

[buletaja]

as days goes By
people forget what PIM is
1st commercialized PIM is eDRAM in X360 that in 2D design
(from outside it is just 20-32GB/sec) from inside is natively Huge BW
X360 has 192 ALU inside the emb RAM = PIM

with big money and multi billion in RD
you can guess the next evolution of eDRAM, 3D ?

people forget that only X1 has GPUMMU
when people like many expert in this forum (maybe)
said GPUMMU just rename of IOMMU LOL
what a simpler answer not based on a fact of course

lets take back on where in begin in 2002-2005

DIVA, PIM (SRAM + ALUs)

IBM Prof Kogge PIM

IRAM (Same BW design like X360 eDRAM, with similar desgin)

X360 1st commercial PIM
limite programmable 192 ALU (about 3CU) + emb RAM

then comes the evolution .....
let said we want to design 3D PIM using SRAM
the 1st logical design is put the faster clocked ALUs (CPU) below SRAM
and then the GPU is clocked low
why need CPU?, like Fine Grained research they insist in the future CP will be bottleneck
they need to put CPU like core, APU is 1st step, the future the integration is more closely
http://research.cs.wisc.edu/multifacet/papers/isca14-channels.pdf
(*,CP replaced by Aggreagator in the AMD research journal above is Simple Out of order 2Ghz CPU)

BTW mike mantor X360 sahder core designer with M.Dogget
also design similar concept Vector ALUs but 1 -2 wide as flexible scalar but has differen Program counter than 16-64wide vector Alus
http://people.engr.ncsu.edu/hzhou/ipdps14.pdf
(make the flex Scalar can do CP like function and Prefetch)

Side Note
===========
many latest PIM design on many journal
they hinted to design as 2 mirroring block
the real extremely high BW PIM will be near the compute ALUs
the coherence 1T SRAM will be near Northbridge

 

[jeff_rigby]

Yep, the hardware has to be there. I am having a having a hard time with this, you cant have magic SW that can run anything without penalty. The idea of VISC makes sense and perhaps it is viable, but it only makes sense to me with specific and radically different HW. "some of it is HW", I just find it completely impossible without huge penalties in speed and capability.

I am not buying some Esram and Jaguar + software can magically transform into a VISC powerhouse.


To me, I dont see a lot of point in thinking of alternate theories of why the Esram is in the xbox one. It doesnt point to some secret capability that will be unlocked one day. I think the xbox without esram would have a much harder time than it does today trying to keep up with the PS4. No need for more far fetched reasons.

First, VISC is on topic only because it's needed by future "more CPUs clocked slower" CPU designs seen in Jaguar, Zen and ARM.

How can we talk about Xbox One Esram like this? Are their people that dont realize the massive bandwidth discrepancy between the PS4 and Xbone? M$ opted for a cheap and slow 8gb of DDR3 while Sony wisely chose Gddr5. No need to make up other reasons, M$ needed a buffer. Just think about it, without esdram, the entire system is at the mercy of the slow ddr3 system ram. The Esram is 3 times faster than the rest of the ddr3 on the system and similar to the speed of the Gddr5 on the Ps4.

The XB1 choice to use DDR3 was not a cost decision. The XB1 ARM block could not use GDDR5 with standby and IPTV power modes, GDDR5 memory draws too much power. For the PS4 to use GDDR5 they moved the ARM block out of the APU and into Southbridge which has it's own DDR3 memory.

Microsoft did need a faster GPU memory cache and tiling which comes with DX12. @Dresdenboy the XB! CPU AND GPU have coherent access to the ESRAM (blue links at the top). GPU is still memory starved but the CPU memory access, like in most APUs, is not as much of an issue....it didn't need ESRAM speeds except for something like VISC but it might have needed coherent memory access between GPU and CPU. Zen CPU in a PC APU design is also to have a 32 MB block of ESRAM and DDR4 memory while the GPU is going to use HBM.

The xbox 360 also has Esram, perhaps this was also a VISC future looking design..... Or maybe the inclusion of Esram in the XB360 helped influence the Esdram in the Xbox one. Their engineers already had experience with such a setup and perhaps parts of their GUI/OS/kinnect/etc functionality was built to take advantage of having a fast and high bandwidth segment of memory. M$ may have planned on trying to emulate the 360 for backwards capability, this could have played a role as well.

The GUI/OS/kinnect/etc , everything (purple and green) on an ARM bus except for the GPU and Jaguar, is ARM and Cadence IP with most of it Xtensa configurable CPU stream accelerators running at 350 Mhz with it's own RAM using uDMA move controllers to move data to and from the 1 Xtensa controller and 32 Cell like SPUs that make up a Xtensa DSP or IVP. The key to the XB1 and PS4 media functionality are those Xtensa processors managed by a ARM trustzone processor (TEE DRM).

Yep, the hardware has to be there. I am having a having a hard time with this, you cant have magic SW that can run anything without penalty. The idea of VISC makes sense and perhaps it is viable, but it only makes sense to me with specific and radically different HW. "some of it is HW", I just find it completely impossible without huge penalties in speed and capability.

Which is the thrust of Dresdenboy's posts. Coming from the proof that the XB1 does have the ability to emulate a Xbox 360 Power PC CPU which is a much scaled down version of the IBM Power PC but still at 3.2 Ghz and for some code, everyone in 2012 was sure Jaguar could not support BC using the Jaguar CPUs at 1.6 Ghz. Is it using two or more CPUs to do this? If so it is VISC like and my point is that in that case it needs that CPU to ESRAM just like Zen will have. And Zen having that ESRAM JUST for the CPU is an indication that VISC will be supported.

I am not saying that Jaguar is an efficient VISC like CPU just that it can support BC even inefficiently. For VISC to be practical for most CPU functions will require changes in how CPUs are designed which may be coming with ZEN. XB1's Jaguar having a custom coherent connection to ESRAM like Zen may mean that 2016 feature was used in the XB1.

A CPU L3 cache is needed just like in Intel CPUs but it does not need to be 32 MB in size...that size points to something else like VISC functionality or ZEN CPUs are so powerful and so fast that they need massively larger L3 cache when used with DDR4 memory. That is unlikely given Moore's law issues and 8 large fast CPUs creating TDP and energy efficiency issues. Zen CPUs are likely smaller simpler CPU in the same design vein and for the same reasons that VISC CPUs are smaller simpler designs.

 

[jeff_rigby]

as days goes By
people forget what PIM is
1st commercialized PIM is eDRAM in X360 that in 2D design
(from outside it is just 20-32GB/sec) from inside is natively Huge BW
X360 has 192 ALU inside the emb RAM = PIM

with big money and multi billion in RD
you can guess the next evolution of eDRAM, 3D ?

people forget that only X1 has GPUMMU
when people like many expert in this forum (maybe)
said GPUMMU just rename of IOMMU LOL
what a simpler answer not based on a fact of course

lets take back on where in begin in 2002-2005

DIVA, PIM (SRAM + ALUs)

IBM Prof Kogge PIM

IRAM (Same BW design like X360 eDRAM, with similar desgin)

X360 1st commercial PIM
limite programmable 192 ALU (about 3CU) + emb RAM

then comes the evolution .....
let said we want to design 3D PIM using SRAM
the 1st logical design is put the faster clocked ALUs (CPU) below SRAM
and then the GPU is clocked low
why need CPU?, like Fine Grained research they insist in the future CP will be bottleneck
they need to put CPU like core, APU is 1st step, the future the integration is more closely
http://research.cs.wisc.edu/multifacet/papers/isca14-channels.pdf
(*,CP replaced by Aggreagator in the AMD research journal above is Simple Out of order 2Ghz CPU)

BTW mike mantor X360 sahder core designer with M.Dogget
also design similar concept Vector ALUs but 1 -2 wide as flexible scalar but has differen Program counter than 16-64wide vector Alus
http://people.engr.ncsu.edu/hzhou/ipdps14.pdf
(make the flex Scalar can do CP like function and Prefetch)

Side Note
===========
many latest PIM design on many journal
they hinted to design as 2 mirroring block
the real extremely high BW PIM will be near the compute ALUs
the coherence 1T SRAM will be near Northbridge

Off topic but interesting. So at the present time PIM logic will be something like a couple of CUs attached to 32MB of sram on one chip with multiple chips on a MCM making a more efficient but a HUGELY more expensive processor block.

While there is a PIM paper with one of the authors from AMD he writes like it is the outlier pointing out one hugely efficient extreme that WON'T be used by AMD. HBM being the cost efficient AMD choice. Resistive Memory is not as temperature sensitive and can change PIM to 10 or so CUs attached to memory making it more practical for Consumer designs. Before that happens we need to transition to all Vector GPUs from Raster, have some way to manage power gating for the multiple blocks and scaling GPU needs.

 

[jeff_rigby]

Sorry Jeff, I don't quite follow- how does ESRAM enable a VISC architecture? VISC requires a CMT-style unified front end across multiple cores, so that it can issue instructions to them all and treat them like a single core if required. The ESRAM is just a high speed scratchpad.

One CPU core with 2 to 4 virtual cores does not require a unified front end. 2 CPU cores requires a shared L2 which Jaguar has. I'm assuming that breaking down code into smaller easy to digest blocks and then scheduling them may require more memory than the L2 cache shared between 4 CPUs.

Everything can be done with a CPU in software but it may not be as efficient as dedicated hardware blocks. Many of the Patents in Dresdenboy's cite are software routines.

 

[ocre]

First, VISC is on topic only because it's needed by future "more CPUs clocked slower" CPU designs seen in Jaguar, Zen and ARM.

The XB1 choice to use DDR3 was not a cost decision. The XB1 ARM block could not use GDDR5 with standby and IPTV power modes, GDDR5 memory draws too much power. For the PS4 to use GDDR5 they moved the ARM block out of the APU and into Southbridge which has it's own DDR3 memory.

Microsoft did need a faster GPU memory cache and tiling which comes with DX12. @Dresdenboy the XB! CPU AND GPU have coherent access to the ESRAM (blue links at the top). GPU is still memory starved but the CPU memory access, like in most APUs, is not as much of an issue....it didn't need ESRAM speeds except for something like VISC but it might have needed coherent memory access between GPU and CPU. Zen CPU in a PC APU design is also to have a 32 MB block of ESRAM and DDR4 memory while the GPU is going to use HBM.

The GUI/OS/kinnect/etc , everything (purple and green) on an ARM bus except for the GPU and Jaguar, is ARM and Cadence IP with most of it Xtensa configurable CPU stream accelerators running at 350 Mhz with it's own RAM using uDMA move controllers to move data to and from the 1 Xtensa controller and 32 Cell like SPUs that make up a Xtensa DSP or IVP. The key to the XB1 and PS4 media functionality are those Xtensa processors managed by a ARM trustzone processor (TEE DRM).

Which is the thrust of Dresdenboy's posts. Coming from the proof that the XB1 does have the ability to emulate a Xbox 360 Power PC CPU which is a much scaled down version of the IBM Power PC but still at 3.2 Ghz and for some code, everyone in 2012 was sure Jaguar could not support BC using the Jaguar CPUs at 1.6 Ghz. Is it using two or more CPUs to do this? If so it is VISC like and my point is that in that case it needs that CPU to ESRAM just like Zen will have. And Zen having that ESRAM JUST for the CPU is an indication that VISC will be supported.

I am not saying that Jaguar is an efficient VISC like CPU just that it can support BC even inefficiently. For VISC to be practical for most CPU functions will require changes in how CPUs are designed which may be coming with ZEN. XB1's Jaguar having a custom coherent connection to ESRAM like Zen may mean that 2016 feature was used in the XB1.

A CPU L3 cache is needed just like in Intel CPUs but it does not need to be 32 MB in size...that size points to something else like VISC functionality or ZEN CPUs are so powerful and so fast that they need massively larger L3 cache when used with DDR4 memory. That is unlikely given Moore's law issues and 8 large fast CPUs creating TDP and energy efficiency issues. Zen CPUs are likely smaller simpler CPU in the same design vein and for the same reasons that VISC CPUs are smaller simpler designs.

Everything in purple and green is on the arm bus, then you go on to say "is ARM and Cadence IP with most of it Xtensa configurable CPU stream accelerators[/URL] running at 350 Mhz with it's own RAM using uDMA move controllers to move data to and from the 1 Xtensa controller and 32 Cell like SPUs that make up a Xtensa DSP or IVP". So "with its own ram", are you still referring to the 8gb ddr3?

I have a huge issue understanding why exactly you would need 8gb of ram for this arm bus in the first place, especially when you starve the gpu as a result. If you absolutely had to have ddr3 for the "arm block" and there just wasn't any way engineers could make use of gddr5 (for some strange reason they lack competence), why not just just a portion of the ram ddr3...... Why all 8gb, which surely will starve your gpu? Then you bring up power consumption as a reason, which i guess is you throwing many things at the wall until something sticks, but here again why can entire PC gpus with gddr5 downclock to sip merely a few watts yet this can't be achieved by engineers designing the Xbox one? We are supposed to just accept these things?

Also, are you suggesting the DSP processors will be used as dedicated HW for VISC on the Xbox one? Hmmmm

You haven't proven to me anything. If m$ had to use ddr3 for arm blocks for DSP, to dedicate the entire 8gb of system ram just seems dumb to me. What you are saying is the entire system was designed around VISC first and the starving gpu just got lucky that esram was also needed for VISC.
I just find that hard hard to believe.

Are you sure that you just didn't read the statement "more CPUs clocked slower" and thought, "hey the apu in the consoles are clocked lower so it's got to be VISC." so since then you have been grasping for anything you can force fit. The Jaguars cores are clocked low and there are a few, but these are x86 cores running at a low speed. The esram, the fact that ddr3 is slow is reason enough to have it. You even admit that, but still in your mind it is part of the plan to one day unlock VISC capabilities for whatever reason. VISC needs super fast cache, so that's why esram is there? That is a stretch to me. You do realize that the Xbox one esram is just slightly faster than the 8gb ps4 gddr5.

Lastly, as others have stated, the Xbox 360 CPU is not all that powerful. The AMD CPU might be clocked low but the 8cores make it more powerful than the xb360. There is no reason why I would find it strange that clever programmers and developers found a way to run some of the xb360 programs on a CPU that is more powerful. You absolutely don't need to dream up VISC as the only way it might be possible. Or at least, I dont

 

[dark zero]

So... XBox One has way more potential than PS4, but no one are exploting that?

Interesting... really interesting...
And VISC could be the future? Could them replace x86, ARM and Power PC eventually?