Why would you assume i/o bottlenecks exist? You should pair a fast processor with an SSD. The IPC of the processor shouldn't change by going from 2 to 4ghz if the architecture is well designed.
Um, I'm not assuming. I'm telling you what theory predicts, what the data shows, and what decades of experience with computing has taught me.
And by I/O, I mean any communication that the CPU does, including with RAM. An SSD can be considered just an added layer of the memory hierarchy.
Umm....in theory there may be some drop off in IPC eventually for the processor as other parts of the design like IMC or cache or System Agent may become bottlenecks.
It doesn't just happen in theory! The bottlenecks are observable at clock speeds achievable now. As mentioned, overclocking a Phenom II does not necessarily increase L3 cache speed, and this has demonstrable damping effects on performance gains. And while this problem doesn't occur with Sandy Bridge (L3 cache runs at core clock frequency for that architecture), the BCLK and QPI speeds still do not necessarily increase.
Now, regarding your theory that IPC changes with frequency. Do you have any evidence to support the view that this is so with either Core i7 or 2nd generation Sandy Bridge designs?
Here, using the exact same Xbitlabs data you used:
Performance per clock is not quite proportionate to IPC, as IPC is normalized per number of active cores, but the trend behavior for each individual processor should be intact.
You will notice that every line is downwardly sloped. If IPC were constant versus clock, the lines would be flat. If IPC went up with increasing clock, they'd slope up. And if there were no correlation, they'd look more scattershot. But no, all the lines slope DOWN. What do you think that means?
SB enjoys excellent scaling in performance with higher clockspeeds.
I am not denying that, and Sandy Bridge is indeed an amazing CPU, but it is not immune to the laws of computation. "Excellent" scaling is not perfect scaling. And to assume IPC to be constant with clock speed is to assume that clock scaling is perfect.
Therefore, it looks to me like we have known data that SB clocks high and its IPC remains intact due to a robust architectural design. As a result, I do not see how you can dismiss IPC in this comparison.
I am hardly dismissing IPC. I am simply saying that IPC does vary with clocks, and sometimes quite widely, so this effect must be taken into account. Look at the i5-760 numbers for Cinebench. Perf/cycle drops from 1.4 to 1.2 going from 2.8 to 4.1 GHz. That's 15%! Obviously this has to be considered if we are talking about 5-10% differences in performance.
Scaling of performance with clock speed is actually another property of processor microarchitectures, and can vary enough between CPUs so that what the performance rankings are at 3 GHz are not necessarily what they are at 4 GHz. As an example, observe the Cinebench numbers where the lines of the i7-950 and the X6 1100T cross!