You want to see the latency Intel has on this gen?
This is what you show those that complained about the CCX latency!
Edit: Sorry, forgot to link the article-
https://www.pcper.com/reviews/Proce...X-Processor-Review/Thread-Thread-Latency-and-
They also talked crap on AMD using the L3 as a victim cache, but said nothing of it when Intel did it, except praise! Duplicity, HA!Am I reading that right and that the latency to every single core from any core is +100ns? If so then yeah the complaints of CCX cross talk is kind of unfounded. Though it probably explains why they decided to up the L2 cache by so much on each core.
I love it. It really shows the genius of the CCX design. If AMD ever decided to go big die, it's obvious that the treating the CPU's and some of the other useful portions like memory controllers as one module was an intelligent decision. They could easily go with a 16 core or even 32 core design die and have tons better latency within the modules. I think MCM is great choice for AMD here. Probably will be for awhile. But they have options and obviously are on the right track.They also talked crap on AMD using the L3 as a victim cache, but said nothing of it when Intel did it, except praise! Duplicity, HA!
But yes, you read that right. Now, even though inter-core comms is slower, it supposedly lowers latency of the cores to other elements on the chip, which is slower with a dual ring design. But that could also be why AMD designed their chip that way with IF. Just love showing the duplicity!!! Thought you would love this news, though!
AMD has smart engineers, just like intel . They knew they couldn't make a monolithic design that would be economically feasible and clock just the same as MCM one . Now they can just pick the best Summitridge dice and mix and match them to form the best perf./watt/mm^2 SKUs, genius decision I must say. They will likely up the core count per CCX in Zen 2, to 6 cores per CCX. This should enable them to compete with whatever intel comes up with their own EMIB solutions. Fun times aheadI love it. It really shows the genius of the CCX design. If AMD ever decided to go big die, it's obvious that the treating the CPU's and some of the other useful portions like memory controllers as one module was an intelligent decision. They could easily go with a 16 core or even 32 core design die and have tons better latency within the modules. I think MCM is great choice for AMD here. Probably will be for awhile. But they have options and obviously are on the right track.
Until i see memory or pci-e latency for core 0 on controller from other chip in the module, i would hold your judgement, you know. After all, there's a good reason eight socket systems are not mainstreamI think MCM is great choice for AMD here.
I love it. It really shows the genius of the CCX design. If AMD ever decided to go big die, it's obvious that the treating the CPU's and some of the other useful portions like memory controllers as one module was an intelligent decision. They could easily go with a 16 core or even 32 core design die and have tons better latency within the modules. I think MCM is great choice for AMD here. Probably will be for awhile. But they have options and obviously are on the right track.
The era of the massive monolithic die is over. AMD just spotted this fact a bit earlier than Intel and designed Zen with Infinity Fabric for this reality. I think the areas which AMD will work on to improve future generations of Zen are
1. Higher Fabric speed
2. Improved cache latency
3. More execution resources and higher IPC.
4. Improved branch prediction.
5. Higher clocks.
I think Zen on 14nm+ will start by addressing higher clocks. I don't know if Pinnacle Ridge could sport higher fabric speeds but its something AMD might look at before 7nm Zen 2. With 7nm AMD will have access to a true high performance node designed for 5 Ghz operation. 7nm Zen 2 should allow AMD to really address a lot of the shortcomings of the current Zen core. I think Intel Icelake on 10+ vs Zen 2 on GF 7LP will probably be the most competitive contest since the Athlon K7 and K8 days.
New information on latency:
Date: April 11, 2017
What you are missing is the latency hit from cross ccx movement in the cache is the infinity fabric latency. They are working on infinity fabric 2 already. This addresses your number 1 and 2. Use of the IBM 7nm addresses number 3 and 5. Number 4 every company does. So it is already being addressed, just a question of IF2 being ready or intermediate advances on IF.
It should be noted that the Alienware Area 51 is built with 2933 ram. So, this means the gap is practically neutral moving between cores, with Intel having a slight advantage. Home built rigs may see higher ram speeds than even 3200MHz AND TR and EPYC are supposed to have an improved interconnect over Ryzen!
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Even with that, that doesn't mean they are not working to improve it.I am not sure AMD has much room to grow on branch prediction. Ryzen supposedly as a high 90s% efficient predictor.
When I said this, I was referring to the rumor from March which said 100gbps Infinity Fabric speeds (same one I pointed to for the B2 revision). The latency is tied to clocks, not absolute time. So, as the speed increases, the latency decreases (in absolute time, not per clock). We also discussed the ES chips for Ryzen having 1:1 DR of the ram speed. If they have the 1:1 of DR, not SR, then the increased speed of the Infinity Fabric will make the latency less of an impact, even though I do agree that the latency should increase to a degree per clock (we'll find out soon). Does it make more sense what I was trying to say previously?TR and EPYC will not have an improved interconnect. Honestly you should probably expect latency to increase when dealing with communication between dies.
Even with that, that doesn't mean they are not working to improve it.
When I said this, I was referring to the rumor from March which said 100gbps Infinity Fabric speeds (same one I pointed to for the B2 revision). The latency is tied to clocks, not absolute time. So, as the speed increases, the latency decreases (in absolute time, not per clock). We also discussed the ES chips for Ryzen having 1:1 DR of the ram speed. If they have the 1:1 of DR, not SR, then the increased speed of the Infinity Fabric will make the latency less of an impact, even though I do agree that the latency should increase to a degree per clock (we'll find out soon). Does it make more sense what I was trying to say previously?
http://www.tweaktown.com/news/56891/amds-12c-24t-16c-32t-cpus-called-threadripper/index.html
"Infinity Fabric can have a bandwidth up to 100GB/S"
So, why are the claims in live report and the table are different? And claims in live report actually make sense (check out with SPECint database).
What are the claims on the live report cant see it?So, why are the claims in live report and the table are different? And claims in live report actually make sense (check out with SPECint database).
Wait, never mind, i need a cup of coffee, could have sworn the numbers on event slide were different.What are the claims on the live report cant see it?
"The connectivity here is set at a bidirectional 42.6 GB/sec per link, at around an average energy of ~2 pJ per bit (or 0.672W per link, 0.336W per die per link, totaling 4.032W for the chip). It is worth noting that Intel’s eDRAM for Broadwell was set as a 50 GB/s bidirectional link, so in essence moving off die in EPYC has a slightly slower bandwidth than Crystalwell. With a total of six links within the silicon, that provides a total of 2 terabits per second of data movement, although AMD didn’t state what the bottlenecks or latency values were."