Originally posted by: XBoxLPU
And by the the time they wait and wait, Intel will have ran circles around them. This isn't intended to come out fan boyish . With the money that Intel has it isn't good to give them time and room to breathe
Not fanboi at all to state the likely outcome of running a two-man race where one guy has 4x the resources to ensure he's eating healthy, has the best trainers, sleeping well and without nary a worry on their mind while the other guy is off in the steppes of Russia ala Rocky Balboa style attempting to make a comeback with the drunk uncle as his trainer and eating raw eggs for breakfast.
Only in this case this isn't the movies...so that part where the underdog doesn't perpetually win every time in real life is kinda a downer.
Originally posted by: ViRGE
The second bit is that given the timetable listed, AMD won't have 32nm products until 2011
http://www.tgdaily.com/images/...shows/200811141/29.jpg
AMD seems to be padding their timeline to allow for some schedule slippage on their end with the design/tape-out/validation and on the Foundry Co's end with getting 32nm production worthy. In the graph above we see the Foundry Co's technology roadmap lists 32nm Bulk as being production worthy end of Q1 2010 and 32nm hi-performance SOI as production worthy at end of Q2 2010.
Note the footnote on lower-left corner of the slide...qual complete means start production so product release would typically be another 3 months after that (90 day cycle time thru the fab for first wafer starts post qual)...so you are looking at a Q2 2010 32nm bulk volume ship and a Q3 2010 32nm SOI volume ship timeline.
Originally posted by: Martimus
If they do start shipping 32nm SOI in volume in 2010, I wouldn't expect that to happen until the second half of the year at the earliest though.
That is in perfect alignment with the roadmap details mentioned above and is very likely to be the internal roadmap that they are targeting, but are sandbagging the analysts by a quarter or two just in case a slip-up occurs in the next 2 yrs.
Originally posted by: Martimus
At the same time, doesn't AMD have a continuous improvement manufacturing environment that may allow them to produce a die shrink earlier, at the expense of other improvements that they would add later to their process? I don't understand the process, as it seems to me that it would add compatibility problems down the line, unless all the added improvements are purely cost and ease of manufacturing improvements. I just remember reading a conversation between you and Viditor about the process, but I really have no true insight into how it works.
CTI -
Continuous Transistor Improvement - enables AMD to make changes to the transistors that impact the transistor's parametrics (leakage, Ion/Ioff, IDsat, IDrive, IDDQ, etc) and/or improve their robustness and lifetime (TDDB, leakage, breakdown, NBTI etc) while doing so in such a way that it does not break the IC design that is being fabbed with the underlying (changing) process technology.
As such you won't see a die-shrink be part of a CTI. You could see something as drastic as the proposed HK/MG interchange for the existing SiON/poly-Si gate stack, but the overall design rules would remain the same (presumably, as a boundary condition to the CTI being deemed viable for implementation to begin with) as otherwise a re-spin of the design would be necessary (i.e. a shrink requires a shrink, no free lunch there).
Where you might get the impression that such things happen, where a shrink happens mid-product life cycle, is from the foundry business structure where they introduce so-called "half nodes" which are intended to be drop-in easy optical shrinks of existing designs. A 45nm design is intended to be drop-in shrinkable to 40nm half-node for TSMC for example.
It's not entirely as "drop it in and forget it" easy as the PR statements make it sound, there is in fact a design respin to ensure bottlenecks are not created (hotspots, current overloads, excessive IR drops, race conditions, etc) but the idea is that if you have an existing and functioning (i.e. low maintenance from design engineer resource standpoint) design at say 45nm then migrating it to 40nm at the same foundry is so crazy easy that you would be a fool to not throw the couple extra millions of dollars of resources that the design team would need to do the 40nm respin/validation efforts.
If the foundry couldn't make it so easy for the fabless guys to take advantage of the half-node then they wouldn't offer it to begin with. And they (TSMC) started offering it as a way to differentiate themselves from the competition (UMC) with the
0.35um node, which then required UMC to likewise offer a half-node to keep their customers from migrating for this specific differentiating feature of TSMC at the time.
A side-note on recent activity with the foundry half-nodes, if I may, it would appear that the foundry's mis-stepped very badly with their 45nm plans and as such the focus shifted quite rapidly to 40nm. Now you hear the foundries discuss the half-node in ways that previously were reserved for the primary node. It is almost as if they couldn't stand to admit they delayed 45nm introduction and instead they just moved the labels around and what was originally going to be the 45nm has been relabelled (and finally introduced after much delay) as the 40nm half-node.
I say this because now the 32nm node is being downplayed, almost as if it were really the 40nm half-node in reality but slipped out a year and relabeled as the 32nm node and instead all the emphasis is on the 28nm half-node now being the "big node" to watch for from the foundries insofar as the introduction of HK/MG, etc. Pure marketing basically.