AMD K10.5 is 10-20 percent faster than K10

[Kuzi]

According to Fudzilla:

Shanghai K10.5 is about 10 to 20 percent faster

I don't know but it seems hard to believe, since from what I read K10.5 is just a die shrink to 45nm with 6MB L3 cache (up from 2MB).

AMD will need every ounce of performance they can get, especially that Nehalem will be released around the same time as K10.5 if not earlier.

 

[brassbin]

competition's good

 

[GFORCE100]

Originally posted by: Kuzi
According to Fudzilla:

Shanghai K10.5 is about 10 to 20 percent faster

I don't know but it seems hard to believe, since from what I read K10.5 is just a die shrink to 45nm with 6MB L3 cache (up from 2MB).

AMD will need every ounce of performance they can get, especially that Nehalem will be released around the same time as K10.5 if not earlier.

Ahh the joy of marketing.

Does it say it will be 10-20% in an exact application? No. This means it will be up to this much faster and more than certain you can bet that the 20% is really the upper limit, and again, this doesn't mean it's in real computing. It's probably based on some synthetic benchmark numbers.

There is a very good reason why such news floats out to the public.

1) It helps a company in trouble improve their share price in cases where its low
2) It helps clear air a little and potentially improve attracting investors
3) It makes the competition counteract more so the troubled company (AMD) can get more of a taste of what the king of the hill has to offer and thus steer its product portfolio more optimally

IMHO the L3 cache on the K10 really isn't the major problem, it's the L2 cache size as 512K per core is really too small for today's applications.

 

[MarcVenice]

Yeah Gforce, that L2 cache has to be to small. I'm sure AMD hasn't tried increasing it's size to see how much performance it would gain them, they must be completely ignorant ? Right ...

I sure hope it's true, but Gforce is right about something, we have to remain sceptical.

 

[GFORCE100]

Originally posted by: MarcVenice
Yeah Gforce, that L2 cache has to be to small. I'm sure AMD hasn't tried increasing it's size to see how much performance it would gain them, they must be completely ignorant ? Right ...

I sure hope it's true, but Gforce is right about something, we have to remain sceptical.

Not ignorant but to put it direct, between a rock and a hard place

On one hand they are in pain over the 285mm2 die size, and on the other if they made the L3 cache too small, then communicating via the cores on the L3 cache level would be severely bottlenecked, especially in multi-threaded apps that uses all four cores in-flight at once.

Intel did the same back with the original Williamette, there was supposed to be a L3 cache in there but it got scraped as at 180nm the size size would have been too big anyway. I believe they settled on a 217mm2 die size at 180nm, which went down to about 175mm2 at 130nm in the Northwood.

I have no doubt that AMD would add more L2 cache if only they could without truly killing themselves in the process (manufacturing nail in the coffin so to speak, 350mm2 die dize

 

[Kuzi]

Originally posted by: GFORCE100
IMHO the L3 cache on the K10 really isn't the major problem, it's the L2 cache size as 512K per core is really too small for today's applications.

If that is really the case then AMD engineers would have designed K10.5 to have 1MB L2 cache per core and 4MB L3 shared cache. The die size should be similar to a 512k L2 per core / 6MB L3 CPU.

I think another reason Phenom was held back performance wise is the fact that the IMC was running slower than the CPU at 1.8-2GHz.

So maybe K10.5 fixes this problem and has the IMC running the same as the CPU clock. This way memory latency will go down and I'm guessing it will scale better at higher clock speeds than Phenom.

We have to wait and see, I hope AMD delivers this time and not make the same disaster with their 45nm process as they did with 65nm.

 

[Idontcare]

Originally posted by: Kuzi
According to Fudzilla:

Shanghai K10.5 is about 10 to 20 percent faster

I don't know but it seems hard to believe, since from what I read K10.5 is just a die shrink to 45nm with 6MB L3 cache (up from 2MB).

AMD will need every ounce of performance they can get, especially that Nehalem will be released around the same time as K10.5 if not earlier.

Intel did it with their Conroe->Penryn transition, it is not implausible that AMD would do it too.

If K10 is considered as being born from a time of complacency in AMD's decision making executive management circles (while K8 was dominating) then you have to agree K10.5 will be born from the fires of a very harried environment for those same decision makers as Conroe has been out for nearly 2 years.

Surely the beatings have been increased in frequency and force until morale improves inside AMD.

The questions, naturally, are (1) what are they doing at the same time to address power consumption at these anticipated performance levels, and (2) does the shrink afford AMD to deliver parts which are performance competitive with the upper half of Intel's Yorkfield SKU's?

 

[Viditor]

Originally posted by: Kuzi
According to Fudzilla:

Shanghai K10.5 is about 10 to 20 percent faster

I don't know but it seems hard to believe, since from what I read K10.5 is just a die shrink to 45nm with 6MB L3 cache (up from 2MB).

AMD will need every ounce of performance they can get, especially that Nehalem will be released around the same time as K10.5 if not earlier.

AFAIK, Shanghai is scheduled for mid 2008, and desktop Nehalem is scheduled for early 2009...

 

[Kuzi]

Originally posted by: Idontcare
Intel did it with their Conroe->Penryn transition, it is not implausible that AMD would do it too.

Yes but the performance gain was more like 7%, not 20%.

I'm sure with more cache and some tweaks K10.5 can get 5-10% gain too, but 20% is hard to believe, unless AMD made many changes to the core.

 

[GFORCE100]

Originally posted by: Kuzi

Originally posted by: GFORCE100
IMHO the L3 cache on the K10 really isn't the major problem, it's the L2 cache size as 512K per core is really too small for today's applications.

If that is really the case then AMD engineers would have designed K10.5 to have 1MB L2 cache per core and 4MB L3 shared cache. The die size should be similar to a 512k L2 per core / 6MB L3 CPU.

The Phenom is 285mm2 at 4x 512KB L2 cache = 2MB + 2MB L3 cache = 4MB total cache. You're suggesting they would have made Phenom at 8MB total cache meaning 570mm2 die size. Never in a million years....the massive die size would kill them as yields would be virtually non-existant at this size and given the problems AMD already has at 65nm with their K8's. At 45nm the die size would still be large.

 

[Kuzi]

Originally posted by: Viditor
AFAIK, Shanghai is scheduled for mid 2008, and desktop Nehalem is scheduled for early 2009...

Shanghai is scheduled for 2nd half 2008, most likely 4th quarter. And knowing AMD, I won't be surprised if the date slips to early 2009.

 

[Idontcare]

Originally posted by: Kuzi

Originally posted by: Viditor
AFAIK, Shanghai is scheduled for mid 2008, and desktop Nehalem is scheduled for early 2009...

Shanghai is scheduled for 2nd half 2008, most likely 4th quarter. And knowing AMD, I won't be surprised if the date slips to early 2009.

Considering the healthy delays the market is seeing in waiting for B3's to be released, your expressed expectation of delays in Shanghai are not outside the realm of mainstream expectation.

AMD's triple-core Toliman processors (Phenom 8000) will be launched on schedule in March this year, initially only B2 stepping versions will be released
http://www.digitimes.com/mobos/a20080226PD214.html

March and still shipping B2's? That doesn't sound like B3 turned out as expected if AMD fully expects to still be releasing B2's in march.

And for anyone who want's to retort "but its digitimes..." I'll refer you to the myriad of digitimes reports all last summer regarding the abysmal clocking and performance of K10 prior to the release of Barcelona. Digitimes gets their info from the people on the ground in the mobo channels, completely different from Charlie's dancing in the hallway spies.

 

[GFORCE100]

Originally posted by: Idontcare

Originally posted by: Kuzi

Originally posted by: Viditor
AFAIK, Shanghai is scheduled for mid 2008, and desktop Nehalem is scheduled for early 2009...

Shanghai is scheduled for 2nd half 2008, most likely 4th quarter. And knowing AMD, I won't be surprised if the date slips to early 2009.

Considering the healthy delays the market is seeing in waiting for B3's to be released, your expressed expectation of delays in Shanghai are not outside the realm of mainstream expectation.

AMD's triple-core Toliman processors (Phenom 8000) will be launched on schedule in March this year, initially only B2 stepping versions will be released
http://www.digitimes.com/mobos/a20080226PD214.html

March and still shipping B2's? That doesn't sound like B3 turned out as expected if AMD fully expects to still be releasing B2's in march.

Well that's one end of the stick, the other, which I personally believe to the most viable one, is that K10 yields have been poor enough to leave AMD with a big load of Phenoms with only 3 fully functioning cores. Now AMD will attempt to shift these as tri-cores to try and recoup some lost finances due to the poor yields. How much can they recoup? Not a lot I reckon, with prices as they are on the Phenoms 4x's and Intel's quad core Q6600, the tri cores need to be below $200 for sure, more like $150. It will be some fresh money for AMD, but nothing write home about.

AMD will scrap the tri-core idea the moment it gets its yields up, be this at 65nm or 45nm. The tri-core idea only surfaced once AMD realized its yields are somewhat poor. They would prefer to sell you a 4 core at a lot more money than a 3 core at considerably less. It really does make a cock-up of AMD's pricing to be honest. The X2's on the low end limit how low prices can go, but on the Phenoms it's the same story. It's not as if the Phenom X4's are priced high.

Not a lot of clever long term thinking at AMD these days me thinks.

 

[Duvie]

The 10-102% is marketing hype, and may actually only represent an extreme they saw in one to 2 test...

I also would temper my expectations on arrival...Like mentioned above the B3 fixed phenoms are rather late, and if they can't get those out I hardly see a quick jump to the new chip...Unless the B3 still has the bug and they want to wash their hands of this whole lineup...

 

[Kuzi]

Originally posted by: GFORCE100
The Phenom is 285mm2 at 4x 512KB L2 cache = 2MB + 2MB L3 cache = 4MB total cache. You're suggesting they would have made Phenom at 8MB total cache meaning 570mm2 die size. Never in a million years....the massive die size would kill them as yields would be virtually non-existant at this size and given the problems AMD already has at 65nm with their K8's. At 45nm the die size would still be large.

Actually I meant that Shanghai K10.5, will have 8MB (2MB L2+6MB L3) cache. So if Phenoms weakness was really the small 512K L2 cache per core, then I'm suggesting AMD engineers would have designed K10.5 to have 1MB L2 cache per core and 4MB L3 shared cache (instead of 6MB), that will still give K10.5 8MB total cache (4MB+4MB) so the die size will be similar to what the actual K10.5 will be at.

 

[SlowSpyder]

Maybe they're comparing the K10.5 to the current Phenom with the TLB bug fix enabled. There's 10-20% just from it working correctly without the TLB bug fix.

 

[VirtualLarry]

Perhaps the 10-20% extra performance was performance that we should have seen with the K10, but it was bottlenecked somewhere. Perhaps they fixed the bottleneck in K10.5.

 

[Idontcare]

Originally posted by: GFORCE100
Well that's one end of the stick, the other, which I personally believe to the most viable one, is that K10 yields have been poor enough to leave AMD with a big load of Phenoms with only 3 fully functioning cores. Now AMD will attempt to shift these as tri-cores to try and recoup some lost finances due to the poor yields. How much can they recoup? Not a lot I reckon, with prices as they are on the Phenoms 4x's and Intel's quad core Q6600, the tri cores need to be below $200 for sure, more like $150. It will be some fresh money for AMD, but nothing write home about.

Ah, working off the excess inventory of existing B2 chips from Q3/Q4 ramp...

Now that would be clever and smart move. I hadn't considered that AMD might be sitting on a large cache of unsold B2's.

But if they are, then fusing off one core and selling them as tri-core's to the desktop market (where TLB is never going to be an issue) is an excellent way to move that inventory rather than take a write-down.

IMO this would constitute a clever move on AMD's part, do you agree?

Originally posted by: GFORCE100
AMD will scrap the tri-core idea the moment it gets its yields up, be this at 65nm or 45nm. The tri-core idea only surfaced once AMD realized its yields are somewhat poor. They would prefer to sell you a 4 core at a lot more money than a 3 core at considerably less. It really does make a cock-up of AMD's pricing to be honest. The X2's on the low end limit how low prices can go, but on the Phenoms it's the same story. It's not as if the Phenom X4's are priced high.

I would expect AMD to at least explore the options of directing tri-cores to the laptop markets with their reduced TDP and improved power management options (versus X2) before entirely abandoning the tri-core model.

It doesn't raise AMD's costs to fuse off a clock-speed limiting or yield-limiting core and resell it as a laptop performance part. It would cost Intel money to sell two wolfdales with one core fused off in an MCM. So AMD does have an opportunity here, not that all opportunity are pursued even if viable, that's where business priorities come in.

 

[Hulk]

I remember AMD touting big performance gains for K10 when it was still on paper. When they tested working silicon much of those gains evaporated. It is entirely possible they figured out what happened and made the fixes necessary in this revision to get back to what they had originally on paper. Or at least to get it working as well as the modeling.

But on the other hand I believe Intel could release Penryn up to 3.8GHz, possibly 4GHz in limited suppiles if they needed to. Even if AMD could produce a miracle and show K10 20% faster per clock and at 3GHz Intel would still have nearly a 1GHz lead on them.

But man that would be great if AMD could pull that rabbit out of the hat! I'm pulling for them.

 

[GFORCE100]

Originally posted by: Idontcare

Originally posted by: GFORCE100
Well that's one end of the stick, the other, which I personally believe to the most viable one, is that K10 yields have been poor enough to leave AMD with a big load of Phenoms with only 3 fully functioning cores. Now AMD will attempt to shift these as tri-cores to try and recoup some lost finances due to the poor yields. How much can they recoup? Not a lot I reckon, with prices as they are on the Phenoms 4x's and Intel's quad core Q6600, the tri cores need to be below $200 for sure, more like $150. It will be some fresh money for AMD, but nothing write home about.

Ah, working off the excess inventory of existing B2 chips from Q3/Q4 ramp...

Now that would be clever and smart move. I hadn't considered that AMD might be sitting on a large cache of unsold B2's.

But if they are, then fusing off one core and selling them as tri-core's to the desktop market (where TLB is never going to be an issue) is an excellent way to move that inventory rather than take a write-down.

IMO this would constitute a clever move on AMD's part, do you agree?

Originally posted by: GFORCE100


AMD will scrap the tri-core idea the moment it gets its yields up, be this at 65nm or 45nm. The tri-core idea only surfaced once AMD realized its yields are somewhat poor. They would prefer to sell you a 4 core at a lot more money than a 3 core at considerably less. It really does make a cock-up of AMD's pricing to be honest. The X2's on the low end limit how low prices can go, but on the Phenoms it's the same story. It's not as if the Phenom X4's are priced high.

I would expect AMD to at least explore the options of directing tri-cores to the laptop markets with their reduced TDP and improved power management options (versus X2) before entirely abandoning the tri-core model.

It doesn't raise AMD's costs to fuse off a clock-speed limiting or yield-limiting core and resell it as a laptop performance part. It would cost Intel money to sell two wolfdales with one core fused off in an MCM. So AMD does have an opportunity here, not that all opportunity are pursued even if viable, that's where business priorities come in.

1) Yes its a clever move but time will show just how financially feasible it is. It's the same tactics supermarkets use virtually every day or on Sundays in terms of bakery product, i.e. it's better to sell bread that's getting old at low low prices than not to sell it at all. This way at least some of the costs get recouped hence lower loss. How well AMD does with selling off the done for B2 Tri cores remains to be seen. The least they expect is to just clear inventory as its somewhat difficult to hide virtually 100,000's CPU's under the carpet once investors start asking questions...and they will sooner or later.

2) I do believe the Phenoms are too hot and power hungry to be putting them in notebooks just yet. This should occur once the 45nm transition is in place. The Phenoms are not only slower than Intel's Core 2 be this Conroe or Wolfdale (and their variants) but also use more power and run hotter. Just look at the 285nm die size again, and at that 4MB of cache on there. Now either AMD a) really uses a lot of transistors for the K10 core or b) they haven't quite refined packing transistors into L2 as well as Intel. Intel has more L2 cache (8MB at 65nm) but still has a considerably smaller die size than AMD. Of course one could say hey stop, aren't you forgetting the IMC. Well to answer that no I'm not. Somehow I don't see that alone needing so many transistors that it really adds so much to the die size, especially as it too is being made at 65nm.

 

[Idontcare]

Originally posted by: GFORCE100
1) Yes its a clever move but time will show just how financially feasible it is. It's the same tactics supermarkets use virtually every day or on Sundays in terms of bakery product, i.e. it's better to sell bread that's getting old at low low prices than not to sell it at all. This way at least some of the costs get recouped hence lower loss. How well AMD does with selling off the done for B2 Tri cores remains to be seen. The least they expect is to just clear inventory as its somewhat difficult to hide virtually 100,000's CPU's under the carpet once investors start asking questions...and they will sooner or later.

The inventory should already be "on the books" for their Q3 and Q4 SEC filings, you can't hide inventory in process nor inventory in warehouses. You can depreciate it as a wasting asset, or you can accelerate the depreciation as a write-down to clear it off entirely.

I wouldn't expect AMD to try and cook the books, although DELL did that for a few years here recently and they still haven't finished restating their earnings. So you just never know I guess.

Originally posted by: GFORCE100
2) I do believe the Phenoms are too hot and power hungry to be putting them in notebooks just yet. This should occur once the 45nm transition is in place. The Phenoms are not only slower than Intel's Core 2 be this Conroe or Wolfdale (and their variants) but also use more power and run hotter. Just look at the 285nm die size again, and at that 4MB of cache on there. Now either AMD a) really uses a lot of transistors for the K10 core or b) they haven't quite refined packing transistors into L2 as well as Intel. Intel has more L2 cache (8MB at 65nm) but still has a considerably smaller die size than AMD. Of course one could say hey stop, aren't you forgetting the IMC. Well to answer that no I'm not. Somehow I don't see that alone needing so many transistors that it really adds so much to the die size, especially as it too is being made at 65nm.

I was speaking more to the idea of creating the 65nm tri-core SKU to sell their languishing B2's and then carry on with the 3-core SKU at 45nm with reduced power consumption. Clearly 65nm tri-cores are not going to make it into laptops. The original K7 Athlons didn't make it to laptops until after the first shrink as well. This is normal for AMD.

 

[heyheybooboo]

Originally posted by: Kuzi

Originally posted by: GFORCE100
IMHO the L3 cache on the K10 really isn't the major problem, it's the L2 cache size as 512K per core is really too small for today's applications.

If that is really the case then AMD engineers would have designed K10.5 to have 1MB L2 cache per core and 4MB L3 shared cache. The die size should be similar to a 512k L2 per core / 6MB L3 CPU.

I think another reason Phenom was held back performance wise is the fact that the IMC was running slower than the CPU at 1.8-2GHz.

So maybe K10.5 fixes this problem and has the IMC running the same as the CPU clock. This way memory latency will go down and I'm guessing it will scale better at higher clock speeds than Phenom.

We have to wait and see, I hope AMD delivers this time and not make the same disaster with their 45nm process as they did with 65nm.

It is my understanding that because of the IMC and expansive memory bandwidth an AMD proc is less dependent upon cache than an Intel proc.

It is my understanding that both AMD and Intel use a 128bit internal data path between cache levels

Somewhere along the road in the last few years AMD also switched from an 'inclusive' cache to an 'exclusive' cache whereby each level contains unique data. Each core of a quad AMD cpu has a 128kb L1 (64K instruction / 64K data) and 512kb L2 - and the cores share the L3 cache.

I believe Intel C2D uses 32 Kb instructions / 32Kb data L1 cache memory for each core. A 2-core 'shares' L2 cache. A 4-core shares 2x L2 cache. I think Intel calls this 'Smart' cache.

Since the P!!!s "Advanced Transfer Cache" Intel cache operates at cpu speed. So Intel's smart cache scales in proportion to clock speed.

I think the problem is that AMD's "Fart Cache" will not scale.

The L3 cache is hung at 1.8GHz - which really sucks because I believe the theoretical design limit is 5.2 GHz. AMD initially said the K10 memory controller's speed can increase as clock frequencies do. Whatever the problem it is not happenning with the current steppings.

What may also be a contrubuting factor is that each AMD core effectively acts independently of the other cores. This in theory is a great idea - independent cores with individual power planes. The downside is that the L3 cache has to manage what may be core0 at full clock and core3 at half speed.

The advantage - as being discussed by IDK - is that an independent core can be disabled creating a tri-core.

The irony in alot of this (from a few rumahs on the internets I've seen) is that core2 on the Phenom may be the core which is not playing well with the other cores

Whether that is FUD or not I have no idea. If someone has a Phenom they could OC core0, core1 and core3 independently of core2 and find out ...

 

[Kuzi]

Originally posted by: GFORCE100
Just look at the 285nm die size again, and at that 4MB of cache on there. Now either AMD a) really uses a lot of transistors for the K10 core or b) they haven't quite refined packing transistors into L2 as well as Intel. Intel has more L2 cache (8MB at 65nm) but still has a considerably smaller die size than AMD. Of course one could say hey stop, aren't you forgetting the IMC. Well to answer that no I'm not. Somehow I don't see that alone needing so many transistors that it really adds so much to the die size, especially as it too is being made at 65nm.

True, Intel are more effecient with their cache, they can stack more cache than AMD can in the same die area. What is interesting is that AMD licensed Z-RAM technology about two years ago, but didn't use it yet.

Z-RAM gives about five times the density of normal cache (SRAM).

Who knows maybe this will be what AMD will use for Shanghai CPUs thus allowing them to have a much smaller die size.

Originally posted by: heyheybooboo
The L3 cache is hung at 1.8GHz - which really sucks because I believe the theoretical design limit is 5.2 GHz. AMD initially said the K10 memory controller's speed can increase as clock frequencies do. Whatever the problem it is not happenning with the current steppings.

I saw some benchmarks a few months ago at xtremesystems forums of Phenom IMC OC'ed to 3GHz, the L3 cache latency went down 15ns or so and performance went up. Don't remember performance was up by how much though.

I'll try to find the post again and link it here.

 

[harpoon84]

Originally posted by: ViditorAFAIK, Shanghai is scheduled for mid 2008, and desktop Nehalem is scheduled for early 2009...

So we can expect Shanghai around June/July then? We shall see, though I doubt it.

Nehalem is due in Q4 2008, although initially only as a high end product, similar to the 45nm QX9650 launch I guess. That still classes it as 'desktop' though.

 

[Extelleron]

Originally posted by: GFORCE100

Originally posted by: Kuzi

Originally posted by: GFORCE100
IMHO the L3 cache on the K10 really isn't the major problem, it's the L2 cache size as 512K per core is really too small for today's applications.

If that is really the case then AMD engineers would have designed K10.5 to have 1MB L2 cache per core and 4MB L3 shared cache. The die size should be similar to a 512k L2 per core / 6MB L3 CPU.

The Phenom is 285mm2 at 4x 512KB L2 cache = 2MB + 2MB L3 cache = 4MB total cache. You're suggesting they would have made Phenom at 8MB total cache meaning 570mm2 die size. Never in a million years....the massive die size would kill them as yields would be virtually non-existant at this size and given the problems AMD already has at 65nm with their K8's. At 45nm the die size would still be large.

It doesn't work like that at all.

Barcelona w/ 2MB L2 + 2MB L3 is 285mm^2, but more of that is logic than is cache. Most of a modern processor's transistors are cache, but remember that cache transistors are much more dense than logic transistors.

It's my estimate that around 70mm^2 of the Barcelona die is the 4MB of cache, with the remaining 215mm^2 being logic. Just looking at the Barcelona die makes this logical - the vast majority of it is the logic, the four cores dominate the cache.

So given that assumption, a Barcelona chip with 8MB Of cache (1MB*4 + 4MB L3) would be around 355mm^2, a far cry from 570mm^2.