[AMD] K12 will be on 28nm

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AtenRa

Lifer
Feb 2, 2009
14,003
3,361
136
Performance wise AMD got beaten so badly.
http://www.anandtech.com/show/5553/the-xeon-e52600-dual-sandybridge-for-servers

Bulldozer failed everywhere for everything.

Get your facts straight,

Intel 32nm Gulftown XEON release date March 2010

AMD 32nm Interlagos (Opteron 62xx) release date November 2011

Intel 32nm Sandybridge XEON release date March 2012

AMD 32nm Delhi (Opteron 63xx) release date December 2012

Intel 22nm Ivybridge XEON release date September 2013
 

Abwx

Lifer
Apr 2, 2011
11,172
3,868
136
Full load clocks are 100Mhz higher. Who cares about clocks for an idle CPU? AMD tried tried that one when they intentionally lowered the base clocks to be able to say they had more turbo. Nobody fell for that marketing tactic.

Full load clocks with 8 cores are 3.6 and 4.0 respectively, if there was only 100MHZ the Mthreaded benches wouldnt look like this, although you are free to keep believing your own lies :








 

ShintaiDK

Lifer
Apr 22, 2012
20,378
145
106
Get your facts straight,

Intel 32nm Gulftown XEON release date March 2010

AMD 32nm Interlagos (Opteron 62xx) release date November 2011

Intel 32nm Sandybridge XEON release date March 2012

AMD 32nm Delhi (Opteron 63xx) release date December 2012

Intel 22nm Ivybridge XEON release date September 2013

And? What part is wrong. SB utterly destroyed Faildozer. And AMD admitted it was an epic failure.
 

Intervenator

Member
Aug 26, 2013
117
7
76
Get your facts straight,

Intel 32nm Gulftown XEON release date March 2010

AMD 32nm Interlagos (Opteron 62xx) release date November 2011

Intel 32nm Sandybridge XEON release date March 2012

AMD 32nm Delhi (Opteron 63xx) release date December 2012

Intel 22nm Ivybridge XEON release date September 2013

3.5 years after Intel mass produces 32nm, 2.5 after 22nm... No tri-gate... And that's assuming K12 comes out Q1 2016? Ugh.
 

Phynaz

Lifer
Mar 13, 2006
10,140
819
126
Full load clocks with 8 cores are 3.6 and 4.0 respectively, if there was only 100MHZ the Mthreaded benches wouldnt look like this, although you are free to keep believing your own lies :

Nevermind, not getting drawn into this anymore.
 
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Abwx

Lifer
Apr 2, 2011
11,172
3,868
136
Okay, then CPU design can increase efficiency by 10% or more?

I talked of a 10% voltage disadvantage, this doesnt translate by 10% more losses but 21%, i said that at equal competences it s a gap that is impossible to close, you ll have to rely on the competition neglecting their design, wich is not a good management model, the exemple of Kabini vs Baytrail is not totaly relevant, not only the CPUs do not work at comparable frequencies for a given performance level but they are both at a point where increasing IPC could still provide a positive return, not so much for high throughput designs like the FX8xxx or the i7, the former has some margin left by virtue of the smaller cores while the latter is already beyond the knee of the curve.
 

Fjodor2001

Diamond Member
Feb 6, 2010
3,938
408
126
I think what's more interesting is what node Zen (next AMD x86 uArch) will be on. My guess is it'll be targeting GF/Samsung 14 nm, since they are designing from scratch.
 

NostaSeronx

Diamond Member
Sep 18, 2011
3,689
1,224
136
If there is any foundation to the 28-nm statement. It sort of follows both TOP-PIM and EUV technologies.
We consider two potential PIM design points geared towards high-performance applications, one in 22nm technology and another in 16nm technology.
GloFo EUV nodes are 22-nm/16-nm/10-nm. This is not to be confused with half pitches.

28/22-nm @ GlobalFoundries+IBM = 90-nm M1 Pitch to 80-nm M1 Pitch (45/40-nm HP)
 
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