AMD launches Ryzen Mobile 7 2700U & 5 2500U with Vega Graphics

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scannall

Golden Member
Jan 1, 2012
1,948
1,640
136
Does anyone think Raven Ridge with 2GB of HBM + dual DDR4 controllers would be a good idea? The Vega iGPU would use HBCC to control caching between main memory and faster HBM.
Please drop the HBM2 stuff for Raven Ridge. Would it be great? Yeah, I'd be all over it. Mark Papermaster, you know the CTO of AMD has said a few times that the cost structure isn't there. They have the designs, but not the price. Will we have Ryzen cores, Vega Gpu and HBM2 this year. No. No way, no how. 2019? Possible. Give that a 50/50. 2020, more likely.

Dreams are great and all. I have a few of my own. But this one isn't coming true this year.
 

msroadkill612

Member
Oct 28, 2009
38
11
81
I think HBCC is already working in Vega, but you don't see a benefit unless the workset is bigger than VRAM.

re:"Hbcc..... Raja says its the most interesting feature but say its 5 years out."

very interesting. I hadnt seen that. I sure find HBCC interesting, especially combined with nvme raid.

as i feared tho, its so revolutionary and rich, it will take years to realise anything like its full potential.

I am still optimistic there will be plenty of low hanging fruit til then tho.
 

msroadkill612

Member
Oct 28, 2009
38
11
81
Large-scale rolluout are always slow, besides EPYC currently lacks racks from major OEMs.

But we dont know any volumes from the secretive mega server world.

It now represents a big chunk of global processor sales, and would be the low hanging fruit for amd, despite protestations of favouring consumers re vega e.g.

if its as popular as it seems, even the pilot installations would max out the budding supply chain.

AMD would be happy to break even or a small loss during this seeding the market stage, so hi volumes needn't neccesarily be reflected in revenue..
 

msroadkill612

Member
Oct 28, 2009
38
11
81
We have seen ryzen evolve from a bit of an ugly duckling in about 6 months.

This will be far more the case in the mobile apu environment.

Even if it only equals intel performance now, RR is a better buy.
 
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Av9114

Junior Member
Nov 29, 2012
21
4
76
The memory bandwidth is definitely going to be a bottleneck. RX 550 has a similar shader throughput with ~3x the memory bandwidth and the 50W TDP includes 4GB GDDR5 so it's not as apples to oranges as it might seem at first glance.

As for HBM, using it instead of DDR for system RAM would actually be preferable for designs where the RAM chips are soldered anyways, if not for the fact that it costs an arm an a leg right now.

You could be right about the memory bottleneck although it seems hard to know for sure until you see how far it throttles under-load. I'd assume that the 550 would be able to sustain something closer to max clocks longer but who knows. As for HBM vs DDR as main system memory, regardless of price I don't think you'd ever want that. HBM is high bandwidth, high latency, which would be devastating for CPU performance. If you have a laptop with an embedded GPU, you've already made a major design decision that indicates that GPU performance is at best the third most important attribute (behind at least CPU and size/thermals/battery life).
 

Av9114

Junior Member
Nov 29, 2012
21
4
76
That's a bit worrying about the lack of LPDDR support. Although how much power does this really save? And does LPDDR come in higher speeds (2400) which is kinda necessary to get decent performance out of the GPU. I thought LPDDR's real advantage is during sleep mode, not really during idle use so worst case we may have to go back to hibernation for long periods of inactivity which kind of sucks, although not as bad since SSD's become standard. My Zenbook can easily sleep for a week and still a few hours left of active use, this almost instant sleep/on mode would be missed.

I'm far from an electrical engineer type so take this with a grain of salt, but given that DDR requires a higher voltage than LPDDR, I'd think it makes a difference any time the machine is on. Sleep is going to be the most pronounced because at that point there's very little if anything using power other than the RAM. As a percentage it matters less as you start to move to heavier loads but I think every bit matters to some extent.

I do suspect that the main reason is related the the memory bandwidth bottleneck for the GPU. If one of your main advantages over Intel is GPU performance you don't want to kneecap your GPU with slower RAM just to save an hour of battery life or whatever. It just seems like on paper you've got a part that's kind of a tweener. It doesn't quite have the GPU performance that you might want but also doesn't quite have the power profile you might want for an ultrabook? If so, then you're still playing the perf/$ game which is fine as it definitely seems lightyears better than before but it's not as exciting. One or two revisions in the future you could have something a lot more attractive though with process and various architectural/platform improvements.
 

maddie

Diamond Member
Jul 18, 2010
4,787
4,771
136
You could be right about the memory bottleneck although it seems hard to know for sure until you see how far it throttles under-load. I'd assume that the 550 would be able to sustain something closer to max clocks longer but who knows. As for HBM vs DDR as main system memory, regardless of price I don't think you'd ever want that. HBM is high bandwidth, high latency, which would be devastating for CPU performance. If you have a laptop with an embedded GPU, you've already made a major design decision that indicates that GPU performance is at best the third most important attribute (behind at least CPU and size/thermals/battery life).
This has been repeated so often as to become fact. The modern world in microcosm.

A Wccftech article using official stats.
https://wccftech.com/jedec-publishes-hbm2-specifications-scale-8hi-32gb-stacks-1-tbs-bandwidth/

tRC:
DDR3 = 4x-5x ns
GDDR5 = 40ns(1.5V) - 48ns(1.35V)
HBM1 = 48ns
HBM2 = 45ns

Comparable to DDR3, so latency is not one of the problems in using HBM2 as main memory.
 
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Av9114

Junior Member
Nov 29, 2012
21
4
76
This has been repeated so often as to become fact. The modern world in microcosm.

A Wccftech article using official stats.
https://wccftech.com/jedec-publishes-hbm2-specifications-scale-8hi-32gb-stacks-1-tbs-bandwidth/

tRC:
DDR3 = 4x-5x ns
GDDR5 = 40ns(1.5V) - 48ns(1.35V)
HBM1 = 48ns
HBM2 = 45ns

Comparable to DDR3, so latency is not one of the problems in using HBM2 as main memory.


As far as I know tRC isn't really a good/proper measure of latency. Again, I'm not hardware/EE type but my understanding is that tRC is more or less a physical property of the DRAM cell which is more or less the same in any memory technology made with the same process (which I think is why they are comparing to DDR3 as it's the most similar to GDDR5?). A more relevant number for DDR4 latency is CAS latency (although not perfect) and for DDR4-2400 that seems to range from 12.5-15ns (this is actually slightly higher than DDR3). I don't know what the comparable number would be for HBM. The big advantage of HBM is that it is physically close to the die which means you can do things that are impractical or impossible with less power than you could otherwise, in this case a REALLY wide memory interface. HBC (Hybrid Memory Cube) is another memory technology that is similar to HBM that is more compute focused targeting HPC/data center use. All of this to say that it probably is possible to use a different memory technology that has both lower latency and higher bandwidth. That technology may even be HBM, although I'd still bet against it, and since the Infinity Fabric is tied to memory clocks it probably won't be soon.


References:
https://www.anandtech.com/show/3851...now-about-sdram-memory-but-were-afraid-to-ask
https://www.anandtech.com/show/9266/amd-hbm-deep-dive
https://www.anandtech.com/show/1196...md-apus-for-laptops-with-vega-and-updated-zen
https://en.wikipedia.org/wiki/Memory_timings
https://en.wikipedia.org/wiki/Dynamic_random-access_memory
https://en.wikipedia.org/wiki/GDDR5_SDRAM
https://en.wikipedia.org/wiki/High_Bandwidth_Memory
 

amd6502

Senior member
Apr 21, 2017
971
360
136
could HBM be practical for smaller video memory configurations such as 2GB to 4GB?

With an APU build 8GB of total system memory used to be fine. These days with firefox having memory leaks and some games being increasingly memory demanding it seems 12GB might start to become the new minimum; not an ideal config as the uppermost 4gb of addresses won't be accessed in dual channel.

16GB of sys memory is quite expensive. So if they could throw 2 to 4gb onto the APU with a memory module as one of the MCMs, could that possibly bring down build cost (by enduser getting away with buying just 2x4gb ram)?
 

Arzachel

Senior member
Apr 7, 2011
903
76
91
As far as I know tRC isn't really a good/proper measure of latency. Again, I'm not hardware/EE type but my understanding is that tRC is more or less a physical property of the DRAM cell which is more or less the same in any memory technology made with the same process (which I think is why they are comparing to DDR3 as it's the most similar to GDDR5?). A more relevant number for DDR4 latency is CAS latency (although not perfect) and for DDR4-2400 that seems to range from 12.5-15ns (this is actually slightly higher than DDR3). I don't know what the comparable number would be for HBM. The big advantage of HBM is that it is physically close to the die which means you can do things that are impractical or impossible with less power than you could otherwise, in this case a REALLY wide memory interface. HBC (Hybrid Memory Cube) is another memory technology that is similar to HBM that is more compute focused targeting HPC/data center use. All of this to say that it probably is possible to use a different memory technology that has both lower latency and higher bandwidth. That technology may even be HBM, although I'd still bet against it, and since the Infinity Fabric is tied to memory clocks it probably won't be soon.

I agree, CAS values would be way more useful, the memory controller would usually hide some of the latency when hitting the same bank twice, as far as I understand. CAS latency is calculated in clock cycles so even if it was equal between HBM and DDR4, the former would take about twice as long than the later in absolute time (DDR4 is dual pumped so clockspeed is half the data rate). But well... it doesn't really matter.

Hitting the main memory takes ages and the actual memory module latency makes up less than a quarter. Having the memory on-package is going to be faster than fetching data off an external bus, so there's a good chance HBM ends up having a lower total memory access time even if the memory modules themselves are slower.
 
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Ancalagon44

Diamond Member
Feb 17, 2010
3,274
202
106
I wonder what the next Ryzen Mobile SKUs to be announced will be?

I mean, I think it is reasonable to expect at least one or two high power, high performance SKUs - 45W SKUs for use in gaming laptops and the like.

But, I also wonder if they will ever release any 5W SKUs to take on Intel's Celeron/Pentium Gold or their Core m series? I saw a slide which said that Ryzen could fit in the power envelope previously used by Jaguar.
 

beginner99

Diamond Member
Jun 2, 2009
5,223
1,598
136
Since HBM2 and interposer are expensive, why isn't AMD just copying intel and putting on some edram to cache the most common access. Seems to bring some huge benefits on intels iGPU.
 

NTMBK

Lifer
Nov 14, 2011
10,269
5,134
136
Since HBM2 and interposer are expensive, why isn't AMD just copying intel and putting on some edram to cache the most common access. Seems to bring some huge benefits on intels iGPU.

Because Intel can manufacture eDRAM chips, and AMD can't.
 

PeterScott

Platinum Member
Jul 7, 2017
2,605
1,540
136
I never thought I would see an Intel CPU with HBM powered graphics before an AMD CPU with HBM...

In a way, AMD contributed to Intel stealing their thunder, by teaming up with Intel to deliever an Intel HBM-GPU solution.
 

Ancalagon44

Diamond Member
Feb 17, 2010
3,274
202
106
I never thought I would see an Intel CPU with HBM powered graphics before an AMD CPU with HBM...

In a way, AMD contributed to Intel stealing their thunder, by teaming up with Intel to deliever an Intel HBM-GPU solution.

I'm also curious about this. I hope that AMD eventually does announce a higher-end APU with HBM2.
 

amd6502

Senior member
Apr 21, 2017
971
360
136
Since HBM2 and interposer are expensive, why isn't AMD just copying intel and putting on some edram to cache the most common access. Seems to bring some huge benefits on intels iGPU.

I wonder if the missing 4MB L3 cache isn't being used for similar GPU cache purpose.
 

LightningZ71

Golden Member
Mar 10, 2017
1,661
1,945
136
I suspect that the missing L3 is because of one of two things:
1) The deliberately reduced the L3 size to 4MB because of the lack of need for the extra 4MB due to the missing second CCX and the change in expected usage profile for the processor. This would save die space for the iGPU.
2) The other 4MB of L3 are present, but disabled on the mobile parts to help the processor meet a power target. It may get enabled on certain higher power parts or on desktop intended SKUs.

I would not expect L3 located in the CCX to be used for caching for the iGPU. Instead, I would expect that the iGPU has it's own internal cache structure.

I am slightly disappointed that the 4MB of L3 aren't there in general for the already released SKUs as I view any measure to ease memory bus contention on APUs to be important and valuable enough to maintain where it isn't cost prohibitive. Keeping the CCX at 8MB L3 should have been trivial. A victim cache is highly desirable in a system that will likely have a saturated memory bus. Prefetching to fill a speculative cache wouldn't help much as it will be rare when the bus will be idle. Maintaining a larger victim cache would mean that requests to that data would be served locally instead of having to queue up for a busy memory bus.
 

formulav8

Diamond Member
Sep 18, 2000
7,004
522
126
I hope that AMD eventually does announce a higher-end APU with HBM2.

May not happen until the cheaper organic interposer from Samsung. Although AMD's current interposer is supposed to be shrunk to a 65nm process and should lower costs. Especially not needing 9 layers anymore. I can't remember off the top of my head where I read this though or I would link.
 

LightningZ71

Golden Member
Mar 10, 2017
1,661
1,945
136
I Don't see AMD doing an HBM apu without doing a different apu layout. The reason that the iGPU in RR is as small as it is, is because it had a hard limit on available memory bandwidth. If you quadrupled the resources in the iGPU without BBM, you'd see very little performance benefit. The same goes with keeping the GPU small and adding HBM. Adding HBM to RR would be a colossal waste of resources for little gain in most cases. Expanding the iGPU in RR to make HBM make sense would make a part that is too space inefficient for the bottom half of the market.

The above reasoning us why I eventually see AMD doing up to 4 different dies at 7nm.
1: 4 CCX, no GCX for Epyc and TR and certain HEDT products.
2: 3 CCX and 1 GCX for desktop HEDT, Epyc and TR products with a "media booster"
3: 2 CCX with 2 GCX for high and mid tier APUs for desktops and laptops
4: half sized 1 CCX with 1 GCX for low power, tablets and thin and light laptops.

I propose this because at that point, AMD will have enough revenue to handle the development of 4 different dies for production at that node. They will be better positioned for their target markets all around. The enabling tech for all of this will be faster memory, such as official support for DDR4 3200 and lpddr 2800 and improved memory efficiency for VEGA as well as the smaller node. The die that I see as least probable is the three CCX, one GCX one as it has the least compelling use case of all of them.
 

IntelUser2000

Elite Member
Oct 14, 2003
8,686
3,785
136
Please drop the HBM2 stuff for Raven Ridge.

I've heard the die doesn't feature an HBM2 controlller. Not having an interface for communicating with HBM2 is a very good reason for why HBM2 won't be used for Raven Ridge.

Also, HBM2 has been only featured in very high end products. Further, none of Nvidia's consumer line has them. The GPU portion would have to be several times larger to justify using HBM.
 

scannall

Golden Member
Jan 1, 2012
1,948
1,640
136
I've heard the die doesn't feature an HBM2 controlller. Not having an interface for communicating with HBM2 is a very good reason for why HBM2 won't be used for Raven Ridge.

Also, HBM2 has been only featured in very high end products. Further, none of Nvidia's consumer line has them. The GPU portion would have to be several times larger to justify using HBM.
I wish I could find that white paper again, but supposedly the memory controller can handle HBM already. Mark Papermaster has said it's something they want to do, and will do when the cost is there. It just isn't there yet.
 
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