Yeah I thought so, but I would assume that some of the experts here, could at least tell me about what order of magnitude we're talking about
Does "bad yields" mean 30% good chips, 50? 10?
What you are asking about involves what we refer to as "functional yield entitlement" in the industry.
Functional yield will vary as a function of the die size (larger die have less yield) and as a function of the background defectivity levels of the fab. Particles that fall on the wafers from the air, etc.
Generally the functional yield entitlement for a given diesize increases as the process node matures.
When a node is just being transferred from development over to production the defectivity levels will be high and the yield entitlement will be low.
This
article gives a nice example of the impact of all this on yields.
There are lots of ways to model yield entitlement. The equation I gave above is a very simplistic version.
Personally I like to use the following equation which captures the effect of "defect clusters" on the yield impact. (makes it a little more "real-world" like if you will)
(note this merely captures the functional yield, actual device yield is further reduced by parametric yield loss thru binning out chips which are too slow clockspeed-wise or consume to much power to hit sellable clockspeeds, etc...as such this equation represents an upper-limit estimate of device yield)
Armed with this equation and some information on the diesize of the particular IC you are interested in you can make a plot of yields for your IC versus D0 (pronounced "dee-zero").
Remember D0 is an indicator of your process node maturity, so it gives you an idea of how badly yields will be at any point during the node maturation timeline.
When we through all this together and compare Juniper and Cypress we get the following:
So now we get a "big picture view" impression of the answer to your question. When a process node is first released to production the defect density levels can be rather large, even larger than 1 DD. This would clearly penalize the yields of a large chip like Cypress, functional yields would be below 10%.
That is why the first chip AMD debuted using 40nm was the much smaller RV740 (137mm^2) as that had much better chances of yielding enough chips to make it profitable to bother trying to sell them.
I took the liberty of highlighting in yellow the region of the chart that most production fabs operate at, some do much better than 0.2 DD but this is sort of the "middle of the road" average across the industry for mature process nodes.
So what is "bad yield"? Depends on the chip size and the maturity of the fab and node. If you have a Cypress-sized chip and it is yielding >50% in a fab with a D0 of 0.2 DD then you are doing all right. If your yields are 20% then you aren't doing all that well, you should be doing better.