AMD Opteron at Newegg

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hans007

Lifer
Feb 1, 2000
20,212
18
81
the opteron from what i know, has 64bit ALUs.



there would be no speed advantages to using 32bit ALUs, it'd be even slower than 32bit code, to hack it to have a 64bit address space like that.


64bit code can run faster. say you have to add 2 64bit numbers. with that much precision its important.


addressing is really the same, thats how x86 compatibility works anyways. on the x86 register level, you have 8 bit registers parts. i.e. say you have a 32bit register , then you have 4 8 bit chunks of it , so it can run older non 32bit code. you can even address these parts.



what x86-64 is doing is extending it one more time, i.e. a 64bit address, is really just 2 32bit words together, with the address of the first word being used .


you could segment them into 4gb blocks to trick old programs into working, etc, by using the first 32bits of the address as your segment addresses.



um...yeah, .... it should be a lot faster at some 64bit code. for 32bit code, i dont really think its gonna be inherently faster, you'll have a lot of gates doing nothing, but adding some leading 0s. the main 32bit speed increases are from the memory controller, improved branch prediction, and probably others speedpath changes, etc. that and the cache, but i dont think the desktop version is gonna have 1mb probably 512k like the barton, so nothing there either.
 

AgaBoogaBoo

Lifer
Feb 16, 2003
26,108
5
81
Originally posted by: kof
Originally posted by: Mrburns2007
1.8 Ghz keeping up with a 3 Ghz cpu is impressive!

Actually, with a properly designed system, 1.8Ghz pushing 64 bits should outdo 3 Ghz pushing 32 bits by 20% ( (1.8*64)/(3*32) ). But I realize that's a "math thingy" many of you might not understand.

I haven't read all the responses but, have you read Anand's articles in which he also mentions that it is because they have a lower number of pipeline stages or something of that sort. The only problem with having less is that it does good in the short run but in the long run not as well because scaling those to higher cpu speeds isn't as easy as if it had more pipelines which is what Intel has.
 

ElFenix

Elite Member
Super Moderator
Mar 20, 2000
102,389
8,547
126
well now it just needs a board and a tremendous price cut.
 

Onepotato

Member
Oct 12, 1999
119
0
0
Take one Opteron, multiply by 400mhz, divide by the square root of Pi, eat some pie, minus six= Tuesday. Dang, that's not right...math thingys@$@#%!
 

frankqfrank

Golden Member
Aug 29, 2001
1,040
0
0
Originally posted by: Onepotato
Take one Opteron, multiply by 400mhz, divide by the square root of Pi, eat some pie, minus six= Tuesday. Dang, that's not right...math thingys@$@#%!

Divide by (monkeys * e)^(weight of your monitor)
 
Mar 14, 2002
54
0
0
Originally posted by: kof
Originally posted by: Mrburns2007
1.8 Ghz keeping up with a 3 Ghz cpu is impressive!

Actually, with a properly designed system, 1.8Ghz pushing 64 bits should outdo 3 Ghz pushing 32 bits by 20% ( (1.8*64)/(3*32) ). But I realize that's a "math thingy" many of you might not understand.

You don't understand computer architecture.

If you're adding two numbers, (5 + 7), you don't use 64 bits. It's still 32 bit integers being added, and a 32 bit result. There's no other way to pipe in additional instructions over the remaining 32 bits (or, in the opteron case, 96 bits).

The speed increase comes from executing more instructions per cycle: even though there's fewer cycles per second, the opteron gets the addition done in fewer cycles (usually, an instruction like addition takes one to two cycles, although there's a few ways to optimize - carry lookahead logic and whatnot, while more complex instructions take 4-6). Other things that speed up instructions are faster busses (get the data to the chip faster, so it has to stall less), which can be achieved through better pipelining and larger L2 caches.
 

ViperV990

Senior member
May 20, 2000
916
0
0
Kinda ironic here... we got Opterons with no boards and Canterwood/Springdale boards with no CPUs.
 
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