Question AMD Phoenix/Zen 4 APU Speculation and Discussion

[uzzi38]

I can finally make this thread.

https://twitter.com/x/status/1519669375283957760

Phoenix is indeed RDNA3. My advice to everyone: treat the old APU rumours as being out of date.

 

[uzzi38]

This diagram is from RGT (I know, I know ), seems like a bit over engineering. View attachment 71768

3 chiplets from 3 process combined as one APU. They do solve the little cache on GPU issue, we shall know more in a month

Phoenix is monolithic.

 

[jpiniero]

We know that AMD has a different spin of RDNA3 for APU mobile and its about maintaining performance in a memory restricted environment by deepening internal caches throughout the WGPs. There is no reason for AMD to even consider using an SLC.

I dunno, to me it seems more like the N33/IGP was more about cost/reducing transistor count than performance.

Phoenix is monolithic.

I dunno, that would mean they would have to port the RDNA 3 IP to N5. And N33 would be alone on N6.

 

[HurleyBird]

So going by this precedence and 7950X official boost clock being 5.7 GHz we can expect AMD to have targeted 5.6 GHz for a HX and 5.2-5.4 GHz for a H Phoenix Point chip

I don't think you can just look at the trend and assume that.

Part of Zen 4 desktop clocking as high as it does is boosted TDPs, which Phoenix is unlikely to. If anything, there's a good chance AMD pushes Phoenix less hard at the top since they already have Dragon Range to cover the DTR segment.

It comes down to three things:

1) The overlapping area between Phoenix and Dragon Range. Only expect one to cover it with real SKUs.

2) Whether the cores in Phoenix are vanilla Zen 4, or some form of Zen 4+ with different frequency characterstics.

3) The specific properties of the 4N node AMD is using for Phoenix. Expect it to be overall better than the 5N node AMD is using for Raphael of course, but we don't know to what extent it is optimized for speed vs. power vs. density.

 

[scineram]

dunno, that would mean they would have to port the RDNA 3 IP to N5.

What are you on about? It's literally 3 weeks away.

 

[jpiniero]

What are you on about? It's literally 3 weeks away.

I guess that's true but Phoenix seems pretty different from N31/N32. Maybe N33's the one that doesn't make sense.

 

[Tigerick]

AMD's Next-Gen Strix Point Ryzen APUs Feature Hybrid 3nm Zen 5 & Zen 4 CPU Cores, Alleges Rumor

AMD's next-generation Ryzen APUs codenamed Strix Point are rumored to feature 3nm Zen 5 & Zen 4 cores in a hybrid architecture package.

wccftech.com

Interesting article for future APU with L4 cache. If AMD manage to make it work with Phoenix Point, I am going to be impressed:

Zen 4 CPU with L1 Cache x 8

1MB L2 Cache x 8

16MB L3 Cache on CCD

32MB L4 Cache on MCD

LPDDR5 memory controller on MCD

 

[deasd]

AMD's Next-Gen Strix Point Ryzen APUs Feature Hybrid 3nm Zen 5 & Zen 4 CPU Cores, Alleges Rumor

AMD's next-generation Ryzen APUs codenamed Strix Point are rumored to feature 3nm Zen 5 & Zen 4 cores in a hybrid architecture package.

wccftech.com

Interesting article for future APU with L4 cache. If AMD manage to make it work with Phoenix Point, I am going to be impressed:

Zen 4 CPU with L1 Cache x 8

1MB L2 Cache x 8

16MB L3 Cache on CCD

32MB L4 Cache on MCD

LPDDR5 memory controller on MCD

Considering this was a 18 months old rumor like 'Zen4 29% IPC uplift', I would take it with a truck load of salt. Especially when it came with silly 'Zen5+Zen4D' hybrid rumor. It seems everybody overestimated something when Zen4 was still on paper.

 

[LightningZ71]

I dunno, to me it seems more like the N33/IGP was more about cost/reducing transistor count than performance.

>it is! Instead of a big block of IfCache, they just added a little L1 abd L2 here and there. Probably cut total xtor count for cache in half at least.<


I dunno, that would mean they would have to port the RDNA 3 IP to N5. And N33 would be alone on N6.

To gain a lot of iGPU performance over rembrandt they will need a lot more transistors. That's going to be quite area intensive on N6.

 

[Kaluan]

Well, we know AMD is pretty adamant about the "Zen philosophy" on mobile when it comes to CPU vs IGP sizes on the die (inside monolithic silicon or otherwise), regardless of nodes used for both or each. They should take roughly the same % out of the complete die/package.

 

[Tigerick]

Here is the solution from AMD that might solve the latency issue of chiplets APU. AMD has SAM (Smart Access Memory) for a year now, aka Resizeable Bar. I don't know it will be implemented on Phoenix Point but it provides me with good thinking out of it: Can PCIe replaces integrated memory controller?

PCIe is a serial bus protocol, so it is cost effective and uses less pin counts. With each new version, the bandwidth keep on increasing: PCIe 5.0 x16 can transfer 63GB/s which is still less than dual-channel LPDDR5-6400 @ 100GB/s. PCIe 6.0 x16 which has been introduced in 2022 doubles up to 121 GB/s finally has enough bandwidth. In fact CXL 3.0 (essential PCIe for DC) has CXL.mem protocol acting like memory extension.

 

[Glo.]

Here is the solution from AMD that might solve the latency issue of chiplets APU. AMD has SAM (Smart Access Memory) for a year now, aka Resizeable Bar. I don't know it will be implemented on Phoenix Point but it provides me with good thinking out of it: Can PCIe replaces integrated memory controller?

PCIe is a serial bus protocol, so it is cost effective and uses less pin counts. With each new version, the bandwidth keep on increasing: PCIe 5.0 x16 can transfer 63GB/s which is still less than dual-channel LPDDR5-6400 @ 100GB/s. PCIe 6.0 x16 which has been introduced in 2022 doubles up to 121 GB/s finally has enough bandwidth. In fact CXL 3.0 (essential PCIe for DC) has CXL.mem protocol acting like memory extension.

View attachment 71932

You can make it easier.

Monolithic: CPU+iGPU die. Chiplet based caches and GDDR6 memory controllers, that both CPU and GPU have access. Chiplets from N31, for example.

128 bit memory controller for GDDR6, with 16 Gbps GDDR6 = 256 GB/s bandwidth.

2.5 times more than 6400 MHz DDR5 memory gives you, and 2 times more than 8000 MHz gives you.

The problem: massively larger power draw, the RAM has to be part of the CPU package(sort of like for M1/M2).

But with cache on the memory chiplets - you solve latency problems, with GDDR6 - you get much, much more memory bandwidth available for the package.

And last problem, the biggest one: who on earth would buy something like that?

 

[DisEnchantment]

https://twitter.com/x/status/1597416676622229504

Looks like PHX won't increase CU count after all.

But very clever concept for Zen 4c in PHX2.
SW in each core sees same amount of L3, just more cores sharing L3 in Zen 4c. Same core, same AVX512, just different clocks.
But 15W seems excessive. AIE and DSP becoming 1st class citizens.

Die sizes gonna be interesting

 

[HurleyBird]

This guy with 34 followers is authoritative?

 

[Glo.]

This guy with 34 followers is authoritative?

Yes. He is.

https://twitter.com/x/status/1597416676622229504

Looks like PHX won't increase CU count after all.

But very clever concept for Zen 4c in PHX2.
SW in each core sees same amount of L3, just more cores sharing L3 in Zen 4c. Same core, same AVX512, just different clocks.
But 15W seems excessive. AIE and DSP becoming 1st class citizens.

Die sizes gonna be interesting

It was going to be 6 WGPs anyway.

It still should have 17% more performance per CU. 5200 MHz DDR5 is ... a little disappointing, to be honest, but as RMB shown each step of DDR5 memory frequency adds 80-100 pts in 3DMark Time Spy graphics score, so its not that big of a deal.

The key will be iGPU clock.

For the small PHX, the only thing that is interesting for me is big.LITTLE implementation.

 

[S'renne]

Btw does this mean we'd be seeing Phoenix Point U series then, even though they showed slides with Phoenix Point as H series only and would be available on...say, Thinkpad T series(flagship laptop models)

 

[TESKATLIPOKA]

He mentioned PHX2 will come late compared to PHX.
Zen4c has similar IPC, only regression will be due to smaller L3.
Zen4c clocks comparable to Zen2, that's good enough.
I thought even L2 would be halved, but It didn't change.
Have to wonder how big Zen4C is.
I don't think 1C2T Zen4+L3 == 2C4T Zen4c+L3.

8C PHX will have 16MB L3.

 

[Tigerick]

Btw does this mean we'd be seeing Phoenix Point U series then, even though they showed slides with Phoenix Point as H series only and would be available on...say, Thinkpad T series(flagship laptop models)

Yes, but unlike current version, upcoming U series going to use smaller die to create Ryzen 3/5 with 2/4 Zen 4 core with 4MB L3 cache and 256 SP RDNA3 graphics. (pending confirmation)

If you are looking for low power and high performance APU, you better looking for current model with 6800U APU. Ryzen 7 6800U has 8 core Zen 3+, 768SP RDNA2, 16MB cache and DDR5 support.

 

[BorisTheBlade82]

Yes. He is.

Care to explain, why?

 

[S'renne]

Yes, but unlike current version, upcoming U series going to use smaller die to create Ryzen 3/5 with 2/4 Zen 4 core with 4MB L3 cache and 256 SP RDNA3 graphics. (pending confirmation)

If you are looking for low power and high performance APU, you better looking for current model with 6800U APU. Ryzen 7 6800U has 8 core Zen 3+, 768SP RDNA2, 16MB cache and DDR5 support.

Well shoot, I am looking forward to getting Phoenix Point, doesn't matter if it isn't low power or not, just hoping it isn't stuck in more expensive laptop models which is why I asked, but thanks anyways, both options are solid..

 

[TESKATLIPOKA]

Well shoot, I am looking forward to getting Phoenix Point, doesn't matter if it isn't low power or not, just hoping it isn't stuck in more expensive laptop models which is why I asked, but thanks anyways, both options are solid.

That will also depend on which one you want. Just look at what Rembrandt laptops are selling for.
It won't be lower than that.
If you are ok with PHX2, then that one should end up in a more budget oriented PCs, but who knows when It will be released.

 

[S'renne]

That will also depend on which one you want. Just look at what Rembrandt laptops are selling for.
It won't be lower than that.
If you are ok with PHX2, then that one should end up in a more budget oriented PCs, but who knows when It will be released.

Good enough, I probably shouldn't be here besides speculating the prices of when it should be available since I don't understand if PHX2's iGPU's worse or equal to Rembrandt laptops, but thanks anyways!

 

[TESKATLIPOKA]

Good enough, I probably shouldn't be here besides speculating the prices of when it should be available since I don't understand if PHX2's iGPU's worse or equal to Rembrandt laptops, but thanks anyways!

You are welcome.
PHX2 will have weaker IGP than Rembrandt.
2 WGPs(4CU) RDNA3 vs 6WGPs(12CU) RDNA2
Of course RDNA3 has higher PPC with likely higher clocks, but at best I think It will perform like 6600U IGP If It can clock 30% higher.
I think they should have used 3WGPs instead. This way It could be also used as a more efficient replacement for Steam deck's Aerith SoC.

 

[poke01]

Man, AMD can rule laptops/console/mobile if they get efficiency right and they are. So happy days ahead!!

 

[jpiniero]

To gain a lot of iGPU performance over rembrandt they will need a lot more transistors. That's going to be quite area intensive on N6.

But doing that gets very costly... especially when OEMs are just going to throw in a 3050 Ti or maybe a 4050.

If that PHX2 is legit, I see it being way more popular than PHX. Especially when you figure that OEMs will mostly use Dragon Range for AMD gaming laptops.

 

[Glo.]

8C PHX will have 16MB L3.

L2 is 1 MB. And that will play crucial role in this version of this arch being in performance between Zen 3 and Zen 4, desktop.

Its fine.