Question AMD Phoenix/Zen 4 APU Speculation and Discussion

[uzzi38]

I can finally make this thread.

https://twitter.com/x/status/1519669375283957760

Phoenix is indeed RDNA3. My advice to everyone: treat the old APU rumours as being out of date.

 

[RTX2080]

I'm curious how to read exact core specification from BONIC? In some old leaks of Zen4 there's also showing 1M L2 and thread count, nothing else:

北森瓦版： “Raphael”のEngineering Sampleが出現する 他

northwood.blog.fc2.com

edit: the only hint/speculation about the core I can find is the original article that InstLatX64 cited:

AMD Phoenix と Phoenix2 の CPUID, GFX1103_R1 と GFX1103_R2 | Coelacanth's Dream

Phoenix と Phoenix2 の CPUID Family/Model/Stepping Felix Held 氏により、AMD Phoenix APU と AMD Phoenix2 APU の CPUID Family/Model/Stepping に関するパッチが Coreboot に投稿されている。 Coreboot はオープンソースなファームウェア、BIOS/UEFI を開発するプロジェク

www.coelacanth-dream.com

Phoenix と Phoenix2 の関係性はコードネーム的にも Raven と Raven2 (Dali/Pollock) に近いものと思われる。

So PHX to PHX2 is something like Raven (RavenRidge APU Picasso) to Raven2 (Dali/Pollock).

 

[TESKATLIPOKA]

12 cores? What kind of config? 4x Zen4 + 8x Zen4c?

 

[BorisTheBlade82]

12 cores? What kind of config? 4x Zen4 + 8x Zen4c?

Wrong labelling. That should be the thread count with a 2+4 config.

 

[moinmoin]

12 cores? What kind of config? 4x Zen4 + 8x Zen4c?

If that's PHX2: 12 threads, 6 cores, 2x Zen4 + 4x Zen4c.

 

[TESKATLIPOKA]

If that's PHX2: 12 threads, 6 cores, 2x Zen4 + 4x Zen4c.

Wrong labelling. That should be the thread count with a 2+4 config.

Ok, thanks.

 

[Exist50]

Imo bound to be the most interesting chip this gen considering how much out from the left field this early hybrid design by AMD comes. Hope we get more insight into it.

I think it's pretty clear that AMD's been itching to go hybrid as well. This is literally their first opportunity with the small core IP being available.

Honestly, it's nice to see them being aggressive for once with their mobile line. Historically they've got the hand-me-downs from other products. Think it's a good omen for future generations.

 

[LightningZ71]

I'm very interested to see how they've made this arrangement make sense. Is it all one CCX, is it two CCXs in our first asymeteic layout (different core counts), and what cells did they use? I suspect that the whole chip is HD, but that they implemented the two performance cores with a lot of extra buffer silicon in-between circuits to enable faster clocks.

 

[Exist50]

Well I have terrible timing. Phoenix got pushed back a month for first availability.

AMD: Ryzen Mobile 7040HS “Phoenix” Laptops Delayed Until April

www.anandtech.com

To align with platform readiness and ensure the best possible user experience, we now expect our OEM partners to launch the first notebooks powered by Ryzen 7040HS Series processors in April.

Doesn't really change anything short term, but if there're delays now, I think it would be optimistic to expect faster than AMD's typical mobile ramp.

 

[moinmoin]

I suspect that the whole chip is HD, but that they implemented the two performance cores with a lot of extra buffer silicon in-between circuits to enable faster clocks.

Yes, that's the assumed difference between Zen 4 and Zen 4c indeed. See also @DisEnchantment's post at

Page 3 - Discussion - Zen 4 Core Specifications Discussion

Page 3 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

 

[TESKATLIPOKA]

Phoenix U APU, not sure what was the actual TDP, most likely 28W. They also mention 3000 points in 3DMark TimeSpy Graphics.
Videocardz

Not bad considering the fastest Rembrandt U managed 11822 points with 27W TDP in Lenovo ThinkPad Z13 G1.
So that's 25% higher MT performance.

 

[Geddagod]

Yes, that's the assumed difference between Zen 4 and Zen 4c indeed. See also @DisEnchantment's post at

Page 3 - Discussion - Zen 4 Core Specifications Discussion

Page 3 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

Zen 4 by default is HD cells.
I think they said 25% of their core are custom cells, so that's prob some custom HP cells that are less dense but high frequency.
Even if they switch everything over to HD idk how much more density they can claw back.
Perhaps they are using even denser cells but idek.

 

[RTX2080]

7940HS

browser.geekbench.com/v6/cpu/624099

https://twitter.com/x/status/1638002986809950209

UserBenchmark: AMD Ryzen 9 7940HS

cpu.userbenchmark.com

 

[Kaluan]

Phoenix U APU, not sure what was the actual TDP, most likely 28W. They also mention 3000 points in 3DMark TimeSpy Graphics.
Videocardz

Not bad considering the fastest Rembrandt U managed 11822 points with 27W TDP in Lenovo ThinkPad Z13 G1.
So that's 25% higher MT performance.

The alleged TS Graphics score tracks with my assumption (@25-28W) of the recent 3000+ score:

Edit: If power scaling is as "generous" as it was with Rembrandt, then (@54W) 25% higher scores in both CPU/iGPU metrics are plausible.

LPDDR5X-7500 setups are MIA for now. And so are SODIMM DDR5-5600 (native support), everything we've had for now I think were just generic 4800MT kits. But at least you can manually upgrade the latter.

 

[trivik12]

https://twitter.com/x/status/1638966730608320513

Framework laptops are modular with good specs. Its expensive for now but does go on sale when next years model release.

 

[moinmoin]

Framework laptops are modular with good specs. Its expensive for now but does go on sale when next years model release.

That's really nice that they finally add an AMD option as well. Considering the prices of Rembrandt laptops and the few Phoenix laptops so far the price is actually pretty decent. For Q3 though...

 

[Geddagod]

2+4 PHX variant clocks in CB23 multicore test

 

[BorisTheBlade82]

View attachment 78648
2+4 PHX variant clocks in CB23 multicore test

Source:

https://twitter.com/x/status/1639864375908642816

 

[TESKATLIPOKA]

View attachment 78648
2+4 PHX variant clocks in CB23 multicore test

So a standard core is ~4GHz and density optimized one is ~2.7GHz in CB23 in this ES model? Let's say TDP is limited to 15W.
The good news is that IPC should be similar, but the standard core is clocked ~48% higher.
You need 3x Zen4C cores to perform as 2x Zen4 cores.
If 4x Zen4C is as big as 2x Zen4 and consumes the same power yet provides ~33% MT performance, then It could be worth It.
If 4x Zen4C are bigger and consume more power, then It's worth using.

 

[DisEnchantment]

So a standard core is ~4GHz and density optimized one is ~2.7GHz in CB23 in this ES model? Let's say TDP is limited to 15W.
The good news is that IPC should be similar, but the standard core is clocked ~48% higher.
You need 3x Zen4C cores to perform as 2x Zen4 cores.
If 4x Zen4C is as big as 2x Zen4 and consumes the same power yet provides ~33% MT performance, then It could be worth It.
If 4x Zen4C are bigger and consume more power, then It's worth using.

Currently it is confusing, why Zen 4c / hybrid in a monolithic die? It is not like it is Zen 4 w/ 100 MTr/mm2 @ 5.7 GHz and Zen 4c w/ 140 MTr/mm2 @5.2 GHz.
Unless FinFlex with N4 is really a thing?

 

[RTX2080]

So a standard core is ~4GHz and density optimized one is ~2.7GHz in CB23 in this ES model? Let's say TDP is limited to 15W.
The good news is that IPC should be similar, but the standard core is clocked ~48% higher.
You need 3x Zen4C cores to perform as 2x Zen4 cores.
If 4x Zen4C is as big as 2x Zen4 and consumes the same power yet provides ~33% MT performance, then It could be worth It.
If 4x Zen4C are bigger and consume more power, then It's worth using.

From the diagram, For Single thread is Zen4 @ 4.6-4.7Ghz and Zen4C @ 3.6-3.7Ghz peak. Under full load the Zen4C part seems limited by power and have much more fluctuate result(2.7-3.7).

 

[naukkis]

Currently it is confusing, why Zen 4c / hybrid in a monolithic die? It is not like it is Zen 4 w/ 100 MTr/mm2 @ 5.7 GHz and Zen 4c w/ 140 MTr/mm2 @5.2 GHz.
Unless FinFlex with N4 is really a thing?

For efficiency. For given performance c-cores will consume less power so hybrid design will be faster overall. Seems that in Phoenix those cores share power domain so at full load both core complexes will stay at their voltage-limited frequency - it can further optimized with own power domains for core groups to give efficiency cores a bit more voltage than high performance ones to balance their clock frequencies to their max efficiency.

 

[Exist50]

given performance c-cores will consume less power

That seems very unclear. They certainly take less area, but if they have a ~GHz penalty, the full fat core should be able to hit the same clocks at a substantially lower voltage. Will be interesting to get more data on for sure.

 

[BorisTheBlade82]

Would be very sad if they shared the same rail.
We need more details, as it would be wrong to assume a 50:50 distribution of TDP for the 2 Zen4 cores vs. 4 Zen4c.

 

[naukkis]

That seems very unclear. They certainly take less area, but if they have a ~GHz penalty, the full fat core should be able to hit the same clocks at a substantially lower voltage. Will be interesting to get more data on for sure.

Full fat core made with potential to high clocks will have lower efficiency at lower clocks despite being able to hit those clocks with lower voltage. Difference is best seen at light loads where both cores probably have similar limit to lowest operating voltage and efficiency core can be many times more efficient than performance one. That's already used scheme with mobile devices where same core is laid differently with power and efficiency use - and power core isn't nowhere near as power-centered as Zen4 is. Efficiency cores are needed for better performance and battery use time for mobile-oriented devices. AMD is in right path there with their efficiency-laid cores.

 

[naukkis]

Would be very sad if they shared the same rail.
We need more details, as it would be wrong to assume a 50:50 distribution of TDP for the 2 Zen4 cores vs. 4 Zen4c.

With same rail both core groups can efficiently share their core-level L3-cache. That might be bigger benefit than performance optimizations with different power rails.