I can finally make this thread.
Phoenix is indeed RDNA3. My advice to everyone: treat the old APU rumours as being out of date.
Phoenix is indeed RDNA3. My advice to everyone: treat the old APU rumours as being out of date.
At iso-voltage, leakage and CaC will be higher for the big core, but at iso-performance, the small core will require substantially higher voltage. We don't have enough information to conclude how those balance out.Full fat core made with potential to high clocks will have lower efficiency at lower clocks despite being able to hit those clocks with lower voltage.
At iso-voltage, leakage and CaC will be higher for the big core, but at iso-performance, the small core will require substantially higher voltage. We don't have enough information to conclude how those balance out.
At iso-voltage, leakage and CaC will be higher for the big core, but at iso-performance, the small core will require substantially higher voltage. We don't have enough information to conclude how those balance out.
This will never ever be the case!With same rail both core groups can efficiently share their core-level L3-cache. That might be bigger benefit than performance optimizations with different power rails.
What makes you think that?At iso-voltage, leakage and CaC will be higher for the big core, but at iso-performance, the small core will require substantially higher voltage. We don't have enough information to conclude how those balance out.
The very strong evidence for separate CCX is that AMD is basically recycling everything - in this case the design blocks from Bergamo and PHX1. They are doing things smarter, not harder.We do know from existing mobile designs that there is crossover point at some performance level - below efficiency cores will win and above performance cores will be more efficient. And that point is quite a high for typical mobile loads. So for mobile devices best performance and battery usage time will need two-differently optimized core groups. We don't yet know AMD core configuration for that Phoenix - but there is basically two possibilities used by ARM. big.Little approach with two core groups - for AMD that would mean different CCX for different groups - or later Dynamic IQ where different cores are laid to same group - to AMD that would mean that both high performance and efficient cores are part of same CCX - and so being able to share their L3 cache too. I don't see point for AMD to go with that older ARM route.
for the APU L3 is already halvedMuch more frustrating is it seems this 'Zen4C' has same size of L3 as Zen4 in PHX2?
Isn't Zen4C being confirmed that it has half L3 of Zen4? How much smaller would this 'Zen4C' than 'Zen4 with half L3 in APUs' ? And afterall the L3 could be globally shared between all cores other than L3 being seperated into two slices/CCX?
Intel/AMD chase the last 10% of performance at the expense of enormous amounts of power. If you limited a Zen 4 chip to 3.7ghz, you will notice power consumption drops like a rock.That seems very unclear. They certainly take less area, but if they have a ~GHz penalty, the full fat core should be able to hit the same clocks at a substantially lower voltage. Will be interesting to get more data on for sure.
for the APU L3 is already halved
for the APU L3 is already halved
This isn't Intel we are talking about. Too early to make that kind of definitive statement.
These are very fundamental scaling trends. It's the same architecture, and thus same IPC. What AMD has done is built a design that sacrifices clock speed for area. This is great if you want to have a whole bunch of cores running near Vmin for max perf/watt, but in terms of per core performance, any point Zen 4 achieves, Zen 4c will need higher voltage (further up the VF curve) to hit, and we all know how badly voltage scaling hurts power.What makes you think that?
Quite the opposite should, and very like will, be true.
Or to be even more specific: No matter the voltages I fully expect Zen4c to get more work done per Joule than Zen4.
This isn't just clipping off the high voltage region; it's fundamentally shifting the entire curve down. If AMD could halve the area just by sacrificing high V support, vanilla Zen 4 would have very little reason to exist in servers, which rarely operate in that region anyway.Intel/AMD chase the last 10% of performance at the expense of enormous amounts of power. If you limited a Zen 4 chip to 3.7ghz, you will notice power consumption drops like a rock.
Now take a density/power optimized chip and test again, power consumption will end up being even lower, especially if the chip is monolithic.
CaC?At iso-voltage, leakage and CaC will be higher for the big core, but at iso-performance, the small core will require substantially higher voltage. We don't have enough information to conclude how those balance out.
Cdyn. AMD calls it "CaC", for whatever reason. Forget what it stands for, but I like adjusting my terminology to whatever the company in question uses, just for fun.CaC?
When you use smaller cells, you need more power for the same performance@Exist50
Sorry, I have to disagree.
Zen4 is clearly a Vmax design, where trade-offs had to be taken - and I am not only talking about density, but consumption on a cell level as well.
If you can make yourself free of that goal, you can take the function blocks and put them in a totally different mask set with different libraries/ cells / constraints / stuff. And that basicall is Zen4c.
Your assumption, that the whole V/f curve might get shifted up is wrong - at least within the relevant boundaries. It will reach higher frequencies at, let's say, up to 3 GHz, with less voltage - the whole characteristics will change.
What you observed with Intel was that they operated Gracemont beyond the window it was designed for - just to win CB23 against the 16c SKUs of AMD. That, and the same voltage rail.
And yes, for stupidly parallel work, Bergamo might win overall against Genoa at ISO-TDP.
You seem to have misinterpreted that chart and the source you got it from - quite the opposite is true.When you use smaller cells, you need more power for the same performance
View attachment 78668
About leakage, I heard different things. I assumed that smaller cells would have lower leakage because the area would be smaller, but I also heard someone say leakage for HP cells are lower than HD cells because more fins create more surface area/volume.
I mean, you can wait for Chips & Cheese to get ahold of it, but halving your inner core area does not come for free. As I said, if the VF curve was truly equivalent up to ~3GHz, then vanilla Zen has very little reason to exist outside of client. 4c would be a miracle core.@Exist50
Sorry, I have to disagree.
Zen4 is clearly a Vmax design, where trade-offs had to be taken - and I am not only talking about density, but consumption on a cell level as well.
If you can make yourself free of that goal, you can take the function blocks and put them in a totally different mask set with different libraries/ cells / constraints / stuff. And that basicall is Zen4c.
Your assumption, that the whole V/f curve might get shifted up is wrong - at least within the relevant boundaries. It will reach higher frequencies at, let's say, up to 3 GHz, with less voltage - the whole characteristics will change.
What you observed with Intel was that they operated Gracemont beyond the window it was designed for - just to win CB23 against the 16c SKUs of AMD. That, and the same voltage rail.
And yes, for stupidly parallel work, Bergamo might win overall against Genoa at ISO-TDP.
Ah shoot, your right, misread the chartYou seem to have misinterpreted that chart and the source you got it from - quite the opposite is true.
IEDM 2018: Intel's 10nm Standard Cell Library and Power Delivery
Presented at the 64th IEEE International Electron Devices Meeting (IEDM) in December, here's a look at Intel's 10-nanometer standard cell library and power delivery system.fuse.wikichip.org
There are a lot of ways to reduce size - increasing density is just one. And please have a look at the quoted Wikichip article as well. Denser cells consume less, not more.I mean, you can wait for Chips & Cheese to get ahold of it, but halving your inner core area does not come for free. As I said, if the VF curve was truly equivalent up to ~3GHz, then vanilla Zen has very little reason to exist outside of client. 4c would be a miracle core.
And this isn't some knock against Zen 4c. It'll do very well for its intended use cases. But there are real engineering tradeoffs behind AMD's choice in product segmentation.
Well hopefully AMD doesn't keep us waiting long for an answer. Also, note that Zen 4 already uses HD cells. There are knobs available other than process.There are a lot of ways to reduce size - increasing density is just one. And please have a look at the quoted Wikichip article as well. Denser cells consume less, not more.
OG Zen4 has its benefits: V-Cache option and higher per core performance for workloads that need that. But for embarrassingly parallel work, my bet is on Bergamo.