AMD post-Bulldozer x86 CPU architecture

[SlowSpyder]

Not very high for simple fact that they are stuck using foundry's that aren't developing high clockspeed process nodes.

I probably worded that a bit poorly. I guess I meant more, what kind of power use they'll aim for more so than if it is likely AMD will go for Intel socket 2055 performance, we both know that would be very unlikely.

But, will these new cores be ~3.5-35 watt parts with their focus on the growing mobile space, maybe a 65 watt top part? Or is there still enough profit to be had to warrant work on a CPU that can be a 125 watt true desktop part?

 

[Phynaz]

Well what about Samsung's 14 nm FinFET process tech that GF will be using according to this article?

You missed the LPE designation. It's low power meant for small SOCs.

 

[ShintaiDK]

I probably worded that a bit poorly. I guess I meant more, what kind of power use they'll aim for more so than if it is likely AMD will go for Intel socket 2055 performance, we both know that would be very unlikely.

But, will these new cores be ~3.5-35 watt parts with their focus on the growing mobile space, maybe a 65 watt top part? Or is there still enough profit to be had to warrant work on a CPU that can be a 125 watt true desktop part?

Looking on their revenue, not to mention R&D budget. It will be very limited. And the main target might actually be embedded. Small cores is the only place AMD can get any money back.

 

[Fjodor2001]

Looking on their revenue, not to mention R&D budget. It will be very limited. And the main target might actually be embedded. Small cores is the only place AMD can get any money back.

Are you suggesting it will be a scaled down cat core, instead of a scaled up one? Does that really make sense, because then they'll be entering ARM territory performance-wise.

 

[Centauri]

Anybody who bought AMD stock the day Jim Keller moved to AMD saw the stock price cut in more than 1/2 before just now returning to breakeven ;-)

Don't be dense. The thread is about a long term product strategy and I'm referring to long term stock price.

 

[mrmt]

Are you suggesting it will be a scaled down cat core, instead of a scaled up one? Does that really make sense, because then they'll be entering ARM territory performance-wise.

Maybe the engineers here could answer this, but if they are planning switchable cores, my guess is that the cores must be somehow close in width, and throughput, otherwise they will end up with wasted resources, meaning a bigger die than it should, or they will end up with a core choked by lack of resources.

 

[Arachnotronic]

Don't be dense. The thread is about a long term product strategy and I'm referring to long term stock price.

I'm not being "dense" -- I'm just saying that hiring a few engineer/manager types doesn't automatically mean that all of the issues that ail AMD will suddenly go away.

AMD's R&D budget is fraction the size of Intel's and in the ARM world, AMD not only competes with Intel trying to play in those sockets, but it is competing with the likes of Broadcom, Marvell, Cavium, etc.

There is NO shortage of smart engineers at any of these semiconductor companies, so to naively believe that hiring a few guys and trumpeting their names at every chance they get is a reason to buy a stock means that AMD's PR hype is working on you.

The bottom line is this: AMD is bleeding MSS in PCs against a much powerful Intel (look at AMD's computing solutions numbers), is a non-player in the traditional x86 server MPU market, has far less GPU share than NVIDIA (even with very competitive products), and is relying pretty much on semi-custom console chips to post half-way decent numbers. On top of all of that, AMD is barely profitable.

So, you can tell us all how it was a no-brainer to buy AMD stock because AMD hired Jim Keller, but anybody who is making investment decisions is going to look at far more than that

 

[hungtran]

Intel is a bureaucracy and AMD is more like a startup. Ideas like HBM gain traction at AMD whereas they would be shot down at Intel. AMD designs and doesn't need to invest in improving fabs. Execution has improved under Rory and Lisa's reign. Don't want to turn this into a stock discussion, but I tend to like to invest in stocks with potential that everyone hates. I think AMD is a good spec play because of all the negativity around it. It's also so cheap that it acts like a LEAP option. Only time will tell if AMD bulls are right, but we're definitely the vocal minority at this point.

 

[Vesku]

The impression I get from conferences is that AMD is just as corporate as Intel. Only with the post Phenom II missteps have I seen the executives start to actually get behind the idea of exploring niches as a coherent strategy. For example they had bought several embedded companies years prior but didn't start to put real effort into the segment until post-BullDozer. Also see their initially slow progress with APUs. Being an outsider I can only speculate that some section of the executives wanted a nimbler company while others were fine with the status quo of existing customers and markets.

 

[hungtran]

I see the consolidation of corporate datacenters, the move of the CPU division to China, the ARM-X86 codevelopment, Mantle and microserver investment as ahead of the curve thinking by management. They're also buying up software companies to speed up HSA adoption by themselves. Sometimes, fighting for your life brings out the best in you.

 

[Vesku]

All very recent developments but yes, AMD does seem to be waking up to the idea that they need to do more than tread water in existing x86 markets. Although that treading water instinct is probably why they are working on a new x86 big core rather than direct those funds elsewhere. In fact I'd say the AMD initiative to deliver both x86 and ARM cores that share the rest of the design is not just about technical engineering but also merging the corporate attitudes.

 

[hungtran]

I loved the Keller quote about how the X86 guys were so happy that they found a bug in ARM only to discover that it was a bug in the bug detection tool. Talk about changing old attitudes.

 

[Fjodor2001]

Maybe the engineers here could answer this, but if they are planning switchable cores, my guess is that the cores must be somehow close in width, and throughput, otherwise they will end up with wasted resources, meaning a bigger die than it should, or they will end up with a core choked by lack of resources.

Yes, switchable cores could be an explanation. But I would more assume they are creating a new big core x86 CPU that will pair well with the existing cat cores. They might even opt for a big.LITTLE type of solution providing good peak performance with good battery life when running low workloads.

 

[Idontcare]

Well what about Samsung's 14 nm FinFET process tech that GF will be using according to this article?

That's low power, not high performance. And 10nm is no different.

 

[Fjodor2001]

In that case I don't see why AMD even bothers designing a new x86 CPU big core. If they will not have anywhere to produce it due to lack of access to suitable process tech, what's the point?

Also, does it mean that Intel will be the only company in the world producing high performance CPUs at 14 nm and beyond?

 

[Arachnotronic]

Also, does it mean that Intel will be the only company in the world producing high performance CPUs at 14 nm and beyond?

IBM will probably continue doing so for its boutique POWER processors. IBM's process is tuned for even higher performance than the Intel processes ;-)

 

[Vesku]

In that case I don't see why AMD even bothers designing a new x86 CPU big core. If they will not have anywhere to produce it due to lack of access to suitable process tech, what's the point?

Also, does it mean that Intel will be the only company in the world producing high performance CPUs at 14 nm and beyond?

Intel has also been tweaking their production for efficiency. Big core does not mean it needs to target high frequency. Read more about the background for BullDozer recently and it seems to me that AMD committed to following Intel's P4 lead, prior to P4 showing its weaknesses, and got so deep in cost wise no executive ever steered the project back to more sensible design goals.

 

[mrmt]

In that case I don't see why AMD even bothers designing a new x86 CPU big core. If they will not have anywhere to produce it due to lack of access to suitable process tech, what's the point?

Big x86 core =! Intel core. AMD might just be aiming at a higher performance/size than their current Puma core, but that's not to say that they will aim for Core performance levels.

 

[mrmt]

IBM will probably continue doing so for its boutique POWER processors. IBM's process is tuned for even higher performance than the Intel processes ;-)

You should write IBM off already. They are going to sell their foundry business, and whoever buys it should not continue to tune the process for performance levels IBM is used to. At most you can expect IBM to pay for a process variant more suitable to their targets.

 

[Exophase]

That's low power, not high performance. And 10nm is no different.

Can you give any insight on how much you expect this process to prohibit high performance? I remember when Intel first released details about Atoms made under a 45nm process tuned for SoCs. They claimed that the impact to performance was only 7%. I'm not sure if I got all of the context of this statement correctly, much less am I sure that the impact isn't greater for newer processes (or maybe more aggressively power tuned ones), but if this means 7% less clock speed then that's necessarily a death knell for Bulldozer-level cores.

I also remember claims that Cortex-A9s were being pushed to over 3GHz on a GF 28nm FD-SOI process that was still intended for mobile - not exactly a record breaking clock speed but much higher than ARM ever advertised, and high considering the fairly shallow pipeline of the design. Curiously, Samsung has announced that they will be providing a 28nm FD-SOI process.

 

[NostaSeronx]

There is no such thing as a low power or high performance transistors. They are only marketed that way for price concerns.

LP = Lowest quality materials, very cheap to manufacture.
G = Highest quality materials, very expensive to manufacture.

FDSOI and FinFETs break the definition of LP and G, as they are both very expensive to manufacture.

 

[Homeles]

There is no such thing as a low power or high performance transistors. They are only marketed that way for price concerns.

While low power processes tend to be cheaper because they forgo thing like HKMG, it certainly isn't true that there's "no difference."

 

[NostaSeronx]

While low power processes tend to be cheaper because they forgo thing like HKMG, it certainly isn't true that there's "no difference."

If you get rid of all the marketing gimmicks they perform exactly the same as the baseline. There is no low power transistor as there is no designing a transistor that way. If you design for low power then that is the device not the transistor. There is no high performance transistors as when you add HKMG, Stressors, you are improving power consumption. Which means high performance is low power and low power is high performance.

Calling a FinFET low power is silly, calling a bulk node with HKMG low power is silly.

20nm-LPM
14nm-LPE
14nm-LPP
20nm-SOC
14nm-FF
14nm-FF+

By definition are all high performance nodes as HIGH PERFORMANCE devices are usually placed on them.

Intel's nodes have been the cheapest of the cheapest while being slightly ahead of the technical implementation curve. Yet, no one calls all of Intel's nodes "Low Power."

You can have a high performance device on any node you want whether it be Poly Si, HKMG, FinFETs, SOI, etc. For those same nodes you can low power devices. Calling something High Performance or Low Power does not mean it is High Performance or Low Power.

The way nodes are marketed by foundries does not correlate to what you can build on that node.

 

[Idontcare]

Not really sure where you are going with this Nosta...physically the transistors are different, and electrically they are different.

The implants are different (both in speciation and in dosage), the isolation spacers are physically different (to engineer the leakage control), etc, etc.

They are independently and separately engineered, sharing little in common in the FEOL outside of subtrate choice.

Vnom is targeted differently, IDDQ is engineered to be different, etc etc. I really don't see how you could make the claims you do above.

 

[NostaSeronx]

Not really sure where you are going with this Nosta...physically the transistors are different, and electrically they are different.

The implants are different (both in speciation and in dosage), the isolation spacers are physically different (to engineer the leakage control), etc, etc.

They are independently and separately engineered, sharing little in common in the FEOL outside of subtrate choice.

Vnom is targeted differently, IDDQ is engineered to be different, etc etc. I really don't see how you could make the claims you do above.

None of that seperates them from the physics limits of the baseline.

Marketing a node with very low leakage as a low power node is completely the opposite of previous generation.

32nm PDSOI/22nm PDSOI = High Performance nodes
14nm FDSOI/10nm FDSOI = Low Power nodes
^-- marketing.

Adding HKMG doesn't make your node high performance it makes it lower power. Calling a FinFET which has pretty high leakage and poor leakage control, a low power node is completely off the walls insane.

You are not increasing Vddnom per generation for higher performing devices with higher leakage, you are decreasing Vddnom per generation for higher performing devices with lower leakage.

Low Power = High Vnom, High power consumption.
High Performance = Low Vnom, Low power consumption.

There is something completely wrong with the foundry industry.

Peak high performance and peak low power can only be on nodes with the lowest power consumption and the lowest leakage.

Thus the nomenclature of nodes are PURELY based on cost of the node.

FDSOI is the cheapest and FinFETs are the most expensive.

28nm-LPS = Lowest Cost
28nm-SLP = Higher Cost than LPS.
28nm-LPH = Higher Cost than LPH.
28nm-HPP = Higher Cost than LPH.
28nm-SHP = Higher Cost than HPP.

While going up the higher cost tree we are seeing lower and lower power consumption. With higher and higher leakage control.

FDSOI and FinFETs break this cost tree;
FinFETs you get weak high performance and weak low power.
FDSOI you get peak high performance and peak low power.

FinFETs drive magnitudes more current to achieve the same clock rates as FDSOI.

Yet, FinFET is the low power node.