AMD pushing SSE5!!!

[ViRGE]

Originally posted by: pm
Doesn't Core 2 Duo achieve something similar to a 3 operand FMAC instruction by using macro-op fusion?

This is a serious question by the way. I am not any kind of microprocessor architect type person and don't pretend to be.

Along with what CTho said, the hardware to actually do a MADD is radically different than just binding together addition and multiplication units. Some GPUs can do a MADD in a single clock cycle, presumably it's going to be something similar for Bulldozer. To my knowledge no current x86 CPU actually has a MADD unit, so the C2D is still doing separate addition and multiplication calculations.

And for whoever said x86 licenses are easy to get, that's not the case. AMD has one as a result of IBM forcing Intel to hand one over. VIA has one because their S3 division holds some very interesting patents that Intel needed for Itanium.

 

[CTho9305]

even if some took multiple cycles to execute and didn't give a speed advantage.

That'd probably be a bad idea. If a CPU reports that it does not support a set of instructions, programs will use codepaths that are optimal using the other available instructions. On the other hand, a CPU that supports those instructions but executes them slowly will get a codepath that isn't optimized for it, and overall performance would likely suffer.

 

[Acanthus]

Originally posted by: Idontcare

Originally posted by: Acanthus

Originally posted by: covert24
what is SSE5 supposed to accomplish? what type of instructions does this have in relation to SSE4?

It's basically "we didnt implement all of SSE4, so we will just tack on some of our own code that doesnt do much and call it SSE5".

In my eyes :thumbsdown:

Who cares what they do or don't do, what they call it or don't call it?

I don't care where performance improvements come from, nor do I care what they are called.

Are you so choosy that you won't buy processor XYZ because of who makes it or what the maker calls it even perchance it gives you more performance per dollar, per watt, per whatever?

I will never understand the premise in these threads that if innovation in one's product is not perceived to be from pristine virginal-like sources and aspirations then it is not worthy of being used to a customer's benefit.

I say bring on SSE5, bring on chips and salsa, bring on 10GHz single-core or 2GHz Octal-core, bring on whatever so long as it means more performance for my applications of interest.

Err, im not really bashing the improvements in SSE5. Im talking about naming it SSE5, when they didnt even (and probably will never) fully implement SSE4.

 

[CTho9305]

Originally posted by: Acanthus

Originally posted by: ObscureCaucasian

Originally posted by: Acanthus

Originally posted by: covert24
what is SSE5 supposed to accomplish? what type of instructions does this have in relation to SSE4?

It's basically "we didnt implement all of SSE4, so we will just tack on some of our own code that doesnt do much and call it SSE5".

In my eyes :thumbsdown:

Anand said it should be the most significant improvement since SSE2.

Time will tell, im just saying what it looks like to me.

Out of curiosity, what is your opinion based on? Do you develop scientific computing / HPC applications / modern game engines / media codec kernels? I don't, so I don't have a good feel for how useful these instructions are to various compute-intensive applications.

 

[Shadowmage]

SSE5 can be described as a compilation of instructions that have been highly requested by major computer companies, like Dell, HP, Apple, etc. I would think that SSE5 would be used quite a bit, especially in the server and HPC space.

Another interesting point. The FMAC instruction doesn't return the same number as a multiply followed by an add. This is due to floating-point rounding.

 

[Acanthus]

Originally posted by: CTho9305

Originally posted by: Acanthus

Originally posted by: ObscureCaucasian

Originally posted by: Acanthus

Originally posted by: covert24
what is SSE5 supposed to accomplish? what type of instructions does this have in relation to SSE4?

It's basically "we didnt implement all of SSE4, so we will just tack on some of our own code that doesnt do much and call it SSE5".

In my eyes :thumbsdown:

Anand said it should be the most significant improvement since SSE2.

Time will tell, im just saying what it looks like to me.

Out of curiosity, what is your opinion based on? Do you develop scientific computing / HPC applications / modern game engines / media codec kernels? I don't, so I don't have a good feel for how useful these instructions are to various compute-intensive applications.

Im really not basing it on anything tangible.

Only AMDs history with things like 3dnow... and the fact that they seem to be covering up SSE4 implementation with "OMGWTF WE HAVE SSE5!"

It couldve just as easily been called 3dnow2, AMDXMO or something else pulled from the sky. They seem to have picked the standard SSE model for a very specific reason.

 

[Mitch101]

Saying someone is a fanboy is the lamest opening statement. As my current main machine is a CORE 2 DUO E6600 with a decent overclock.

 

[ViRGE]

Originally posted by: Acanthus
Im really not basing it on anything tangible.

Only AMDs history with things like 3dnow... and the fact that they seem to be covering up SSE4 implementation with "OMGWTF WE HAVE SSE5!"

It couldve just as easily been called 3dnow2, AMDXMO or something else pulled from the sky. They seem to have picked the standard SSE model for a very specific reason.

Technically it is a SSE extension, it's using the SSE register set just like any other version of SSE. 3dnow wouldn't have been a fitting name since it's not an extension to such, but they still could have named it SSE-something, without calling it SSE5.

 

[evolucion8]

Originally posted by: keysplayr2003

Originally posted by: ahock
what if Intel will release SSE5 in Nehalem processor? I gues they will have since its a new architecture..... My take SSE is already for Intel although they are open standard. AMD should name it otherwise and prove to the industry that what they develop is worthwhile. This is to avoid confusion on the said instructions. Bad thing is SSE5 AMD is proposing are not backward compatible with most of SSE4. Tsk tsk tsk......

You mean something like "3DNow"? Or 3DLater... sorry, it was so there.

LMAO, 3DLater, I almost fell over the chair when I saw that joke, loll, it's like SSE, Screaming Simd Exception - Simple Illness Multiple Doctors