The "NB" is integrated into the APU die, and has been for years. Any extra memory bandwidth would need to be attached through the FM2+ socket... which doesn't have the pins for it.
Since when have AMD been more interested in desktops? Could you provide a link to this hint Rory dropped? Or are you basing this off Kaveri launching on destops first? I find it very hard to believe the desktop side of the business is showing more promise than mobile
AMD Q313 Q&A said:http://seekingalpha.com/article/175...anscript?all=true&find=advanced+micro+devices
Romit Shah - Nomura
And the competing results are my biggest concern looking at the quarter, and Rory, you talked [ph] to the weakness to just general softness in consumer notebooks. But if I look at your numbers, the computing business was down 6% sequentially, so desktops were up, which means notebooks are probably down more than 10% and I compare that to Intel whose PC business was up, I think mid single digits and are you seeing Gartner were also up. So how do we reconcile the difference between AMD’s consumer business, notebook business and Intel and just the general market?
Rory Read - President and CEO
I think you kind of summed it up properly. The consumer market is feeling more pressure, but all parts of the PC markets are down. This market, this industry is down 10% and at rates it’s never experienced before. It’s going to continue.
From our perspective, AMD is over index the client notebook. We have always been. We have had, just like we have to diversify our portfolio across high-growth segment, we need to diversify this core business. We need to move stronger into desktop and as we talked about a year ago, we worked on the inventory on the desktop segment and we built and repaired that and we have seen two quarters of consistent revenue growth in that segment and we believe that we have the right product stack to continue to make progress and that’s part of our business as well.
2M/4C makes more sense anyway with Steamroller removing the CMT penalty. The only real use for octo core FX's is being able to load 1 execution unit per module to avoid said penalty.
The L3 is useless for consumer workloads (from AMDs own mouth) so whats the point in producing those enormous dies when they'll only sell for $200.
To actually remove the CMT penalty AMD would have to get rid of CMT itself, no? If you are talking about mitigating the CMT penalty then that would mean beefier cores and less sharing, making it much more like a conventional architecture.
I think it's correct to say that AMD L3 slow cache is useless for consumer workloads.
FPU and SMIDs are also shared.
FPU is shared in a sense. The FPU is actually 2x 128-bit FMACs which can work independently of each other, or combine as 1x 256-bit FMAC for AVX instructions.
Bulldozer = 4+ macro-ops to one different core every other cycleDepend on the Decode and Dispatch capabilities of SR. I don't know if SR can decode and dispatch up to 5+ uops simultaneously (int cores have 4 ports). Also, do you know if the FPU can start 1 FP + 1 MMX op simultaneously?
G Also, do you know if the FPU can start 1 FP + 1 MMX op simultaneously?
IOMMU 2.0(Windows only HSA)What we know about PUMA+ cores right now?
Only because AMD wants to move stream processing apps to the iGPU, IMHO. Other than that, there are not allot of apps in general use that are FP heavy, but those that are do suffer from no L3$. Hopefully, AMD's L2$ didn't lose much performance going to 4 MB (though that hard to believe given cache performance wasn't one of AMD's strengths).
Only because AMD wants to move stream processing apps to the iGPU, IMHO. Other than that, there are not allot of apps in general use that are FP heavy, but those that are do suffer from no L3$. Hopefully, AMD's L2$ didn't lose much performance going to 4 MB (though that hard to believe given cache performance wasn't one of AMD's strengths).
I'm rather curious to see whether AMD improved cache hit rates or if they went for yet another brute force solution, just throwing more transistors at the problem.
That is such a weird expression. I always took over index to mean that you've got more than enough of something. If that's what he means then he's saying they have their bases more than covered and can focus elsewhere, which is obviously wrong as they aren't exactly killing mobile right now. AMD need Kaveri in the mobile space pretty badly actually. Speak English RoryFrom our perspective, AMD is over index the client notebook.
From where did you get this? This is not in agreement with data we have so far (given by AMD publicly) nor we have any updates on GCC that support such pipeline organization.x86 Steamroller cores have 8 ports, 4 EX and 4 AGLUs.
FPU is shared in a sense. The FPU is actually 2x 128-bit FMACs which can work independently of each other, or combine as 1x 256-bit FMAC for AVX instructions. In comparison, K10 had 1x128bit FPU per logical core.
this is completely incorrect.
K10 had 3x 128bit FPU/SIMD units per core. it had one ADD one MUL and one MISC.
bulldozer has 2x 128 bit FMA FPU's and 2x 128 SIMD/MMX per module.
So bulldozer has less peak resource per core then K10 in FPU but more flexibility. Bulldozer is very strong in mixed FP/SIMD workloads where it can get good execution across all 4 units.
Also bulldozer doesn't do 256bit ops over both FMA units, that would create scheduling hell. it does 256bit ops as two instructions over the same 128bit unit. remember the only different between 128 bit and 256 bit here is that there are 4 vs 8 32 bit floats.
That is such a weird expression. I always took over index to mean that you've got more than enough of something. If that's what he means then he's saying they have their bases more than covered and can focus elsewhere, which is obviously wrong as they aren't exactly killing mobile right now. AMD need Kaveri in the mobile space pretty badly actually. Speak English Rory
which is why i said FMA and more flexible :awe: to be able to execute FMA but not MUL or ADD is going back a long way in CPU history.BD units can each do both FMUL and FADD while K10 units
are capable of only a kind of operation per unit , not counting
FMA wich double the throughput on some instances.
one X86 op. two internal OP's (MOP's). they are broken into two MOP's and executed as 2 128bit ops. just like SSE was done on A64 (2x64 for 128). Also if you go back and watch the original Bulldozer hotchips presentation the presenter specificity says that the FPU is doublepumped for 256bit ops.A 256bit op is executed as a single instruction using
the two 128bit units wich can be used as a single
256bit exe unit, besides FMA has nothing to do with AVX.
Supports AVX instructions. Intel announced the AVX instruction set extension in 2008 and the AMD designers have had very little time to change their plans for the Bulldozer to support the new 256-bit vectors defined by AVX. The Bulldozer splits each 256-bit vector into two 128-bit vectors, as expected, but the throughput is still good because most floating point execution units are doubled so that the two parts can be processed simultaneously.
i dont know why you quoted me because nothing you said has anything to do with what i said and where you tried to tell me i was wrong you were flat out wrong............
but if you dont believe me i will quote the guru
http://www.agner.org/optimize/blog/read.php?i=187
Also bulldozer doesn't do 256bit ops over both FMA units, that would create scheduling hell. it does 256bit ops as two instructions over the same 128bit unit. remember the only different between 128 bit and 256 bit here is that there are 4 vs 8 32 bit floats.
A 256bit op is executed as a single instruction using
the two 128bit units wich can be used as a single
256bit exe unit, besides FMA has nothing to do with AVX.
Supports AVX instructions. Intel announced the AVX instruction set extension in 2008 and the AMD designers have had very little time to change their plans for the Bulldozer to support the new 256-bit vectors defined by AVX. The Bulldozer splits each 256-bit vector into two 128-bit vectors, as expected, but the throughput is still good because most floating point execution units are doubled so that the two parts can be processed simultaneously.
I haven't really seen any hard evidence of their being any real kind of penalty. I don't remember Trinity vs Zambezi comparisons showing any regression. AMD did mention that L3 is useful for server, but weren't specific about what kind of server workloads.
Also, Trinity/Richland already have 4mb L2 (2mb/module) so they aren't losing anything thereAside from dynamic resizing of the L2 I don't think cache has been touched
It was slower than the IMC bandwidth wise while latency was faster than the IMC.This makes their design choice even more confusing since L3$ was slow as was the IMC.
fixed.What would be correct to say is that x86 Steamroller cores have 8 ports, 4 EX and 4 AGLUs.
There will be two more 15h architectures after Excavator.If Excavator is the last big core they plan to design they probably won't bother attempting to fix it at all.
The two L2 caches from the CPU and GPU are coherent by a 256-bit interconnect.As for L3, it would be interesting to have on an APU if it was also addressable by the GPU
BD/PD partitioned the L3$ into a 2MB/module cache, the same size as L2$ - so the advantage of having a large L3$ was somewhat lessened. This makes their design choice even more confusing since L3$ was slow as was the IMC. I can't recall the exclusivity/inclusivity of the L3$, but it wouldn't have been very effective if it was being used as a victim cache at that size ratio (1:1).