BoFox
Senior member
- May 10, 2008
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GK110 being "nearly" 30% bigger (actually less) means that Hawaii will be over 423.8 mm^2, no less.
This DOES make it the biggest GPU silicon AMD (or ATI) has ever made, beating HD 2900XT at 420mm^2.
This also means that it will be at least 20% bigger than Tahiti's 352mm^2.
It seems that:
15-25% more shaders/TMUs
and
48 ROPs
(or even more shaders/TMUs while still having only 32 ROPs which might hurt @ higher resolutions with AA)
is just about what AMD can do with this increase in silicon die size, without some other magical optimizations or expansions (remember, HD 4890 was actually LARGER than HD 4870 despite having practically identical GPU layout).
It certainly does seem like 30% increase in performance is not out of reach, as long as AMD is willing to allow a 300W TDP headroom on this single-GPU card.
However, I'd expect a modest TDP ceiling, and a 20% increase out of the box rather than 30%... because going anywhere close to 300W is just pushing it too hard. There are too many risks (longevity, warranty, noise, notoriety of heat output, etc..) for this to become a practically viable option.
25% increase at 265W might, just might be possible. AMD did it really nicely with Bonaire, after all, so I think they can do it (hint, that is, beat GTX 780).
.. I'm just hoping that AMD will no longer stubbornly stick to 32 ROPs, and just move onto a symmetrical ratio of 48 ROPs to 384-bit bus (so that there's full access to the RBEs rather than limited crossbar access). That's why Tahiti's 384-bit bus seems rather lackluster, like as if the GPU had less than 320-bit bus access in the real world. Just guessing - there seems to be about 5% overall performance overhead that could be regained due to having a straight 48 ROP design alone. Yet it would probably also translate to 5% increase in silicon die size as ROPs are notoriously difficult to shrink with each new fab process nodes, from what I have been told. After all, it was a logical move by AMD to do that with Tahiti early on 28nm process in order to get it out ASAP while keeping the size and power consumption down. I have no idea on exactly how much the ROPs affect power consumption though (up to 5 percent for this 50% increase in ROPs??).. but if AMD manages all of this well (48 ROPs, +25% performance, say 15+% reduction in power consumption-to-performance ratio, etc..) then I'd be amazed! Or more!!!
This DOES make it the biggest GPU silicon AMD (or ATI) has ever made, beating HD 2900XT at 420mm^2.
This also means that it will be at least 20% bigger than Tahiti's 352mm^2.
It seems that:
15-25% more shaders/TMUs
and
48 ROPs
(or even more shaders/TMUs while still having only 32 ROPs which might hurt @ higher resolutions with AA)
is just about what AMD can do with this increase in silicon die size, without some other magical optimizations or expansions (remember, HD 4890 was actually LARGER than HD 4870 despite having practically identical GPU layout).
It certainly does seem like 30% increase in performance is not out of reach, as long as AMD is willing to allow a 300W TDP headroom on this single-GPU card.
However, I'd expect a modest TDP ceiling, and a 20% increase out of the box rather than 30%... because going anywhere close to 300W is just pushing it too hard. There are too many risks (longevity, warranty, noise, notoriety of heat output, etc..) for this to become a practically viable option.
25% increase at 265W might, just might be possible. AMD did it really nicely with Bonaire, after all, so I think they can do it (hint, that is, beat GTX 780).
.. I'm just hoping that AMD will no longer stubbornly stick to 32 ROPs, and just move onto a symmetrical ratio of 48 ROPs to 384-bit bus (so that there's full access to the RBEs rather than limited crossbar access). That's why Tahiti's 384-bit bus seems rather lackluster, like as if the GPU had less than 320-bit bus access in the real world. Just guessing - there seems to be about 5% overall performance overhead that could be regained due to having a straight 48 ROP design alone. Yet it would probably also translate to 5% increase in silicon die size as ROPs are notoriously difficult to shrink with each new fab process nodes, from what I have been told. After all, it was a logical move by AMD to do that with Tahiti early on 28nm process in order to get it out ASAP while keeping the size and power consumption down. I have no idea on exactly how much the ROPs affect power consumption though (up to 5 percent for this 50% increase in ROPs??).. but if AMD manages all of this well (48 ROPs, +25% performance, say 15+% reduction in power consumption-to-performance ratio, etc..) then I'd be amazed! Or more!!!
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