There is no such thing as "Lumpy Ridge." AMD is not using 22nm SOI. These are completely unsubstantiated claims that fly in the face of everything that AMD executives have said publicly about their products and their strategy.
"Lumpy Ridge?" And this looks something like a reiteration of Stoney Ridge on a process designed for high performance. Interesting idea...Intel's all but stopped putting much into its Celeron and Pentium versions of the Core chips.
Those are not my expectations. Those are just possibilities, that can occur in upcoming months.
Partial Speculation, not 100% sure:
Raven Ridge - 14nm High Performance SoC(14HP w/ 14LPP+ BEOL) -> Quad-core/8T(Max SKU). (Super-4W (4w to 65w)) (14LPP to 14HP shuttle)
Lumpy Ridge - 22nm Ultra Low Power SoC(22FDX-ULP w/ 28HPA BEOL) -> Dual-core/2T(Max SKU?). (Sub-10W(1.5w to 10w)) (Micro- prefix returns) (28nm to 22nm shuttle)
Why don't you write in normal, human sentences?Partial Speculation, not 100% sure:
Raven Ridge - 14nm High Performance SoC(14HP w/ 14LPP+ BEOL) -> Quad-core/8T(Max SKU). (Super-4W (4w to 65w)) (14LPP to 14HP shuttle)
Lumpy Ridge - 22nm Ultra Low Power SoC(22FDX-ULP w/ 28HPA BEOL) -> Dual-core/2T(Max SKU?). (Sub-10W(1.5w to 10w)) (Micro- prefix returns) (28nm to 22nm shuttle)
-> Raven Ridge => 4266 MHz support @ 1.35v/1.4v (14nm SOI node)
-> Lumpy Ridge => 4266 MHz support @ 1.05v/1.1v (22nm SOI node)
How so?No. This is all false.
I'm not human? Joking, of course. The reason is that it becomes a bore. Why do the below, when I can simply condense the post.Why don't you write in normal, human sentences?
The current CCX structure doesn't allow for sole single-core, dual-core, or triple-core operation. There can only be quad-core or octo-core.Seems that the average joes doesn't understand the engineering terms.
So Nosta, are you saying that the Sub-10 Zen cores will have only 2 Cores and 4 threads ala Core M, but targeted against Atom? And at 22 nm ala Haswell?
Maybe another Moorefield to smartphones?
Oh snap, it is possible. Just went looking backSeronx there is one thing that you should have add. Raven Ridge means that the GPU in the APU also have to be made on the same node. So Vega/Raven Ridge will have to also use the same node, if your information are correct.
Secondly, are you confident that there will not be 95W version of the APU with 4 cores, 2 GB of HBM2, and more than 16 CU's for GPU?
How so?
I'm not human? Joking, of course. The reason is that it becomes a bore. Why do the below, when I can simply condense the post.
I have found partially successful invocations of sources which leads to partial speculation of that; (No, you will not be seeing the aforementioned sources)
Raven Ridge will be on a 14nm SoC node. In particulate, it will be a High Performance node that just happens to be SOI FinFET. .
There is typically no source for online forum meanderings/speculation. Just plenty of free time for some users to be incessantly googling.
The only people who overcomplicate things are those who typically don't understand them. At all. They only fool the lay.
"If you can't explain it simply, you don't understand it well enough"
Sent from HTC 10
(Opinions are own)
Definitely. But they never overcomplicate simple matters and try to dumb down complex too.There are gems online (see: Beyond3D forum information about Pascal GPU launches), but you have to learn to sort the wheat from the chaff.
I don't wish to attack any particular poster at all and really welcome the involvement of all. Nosta seems knowledgeable and I'd just like to be able to read his posts. Maybe I could learn something. That's allOh look it's mr word salad Nosta Sternox posting totally made up nodes and architectures. What an interesting read that gibberish is. He might as well post the instruction manual to his Keurig.
Personal attacks are not allowed
Markfw900
Anandtech Super Moderator
Launches with Cannonlake, shortly after Coffee Lake.So what is the current estimate of a release date for a Zen powered APU?
So what is the current estimate of a release date for a Zen powered APU?
Horned Owl is a variant of next year’s Raven Ridge mainstream APU... A version of Horned Owl will be offered for the AM4 socket. Expect to see Horned Owl in late 2017.
Globalfoundries Preps 12nm FDSOI Process
Globalfoundries Inc. has announced a next-generation FDSOI process to follow on from the 22FDX process that is nearing production. The company has also announced the presence of EDA and IP companies Cadence and Synopsys within the FDXelerator ecosystem development program for FDSOI.
FDSOI, standing for fully depleted silicon on insulator, is an alternative to the FinFET chip manufacturing style favored by Intel and foundry TSMC. Much of the original research for SOI was conducted by IBM before being carried forward by STMicroelectronics. Now Samsung at 28nm and Globalfoundries at 22nm are working to bring FDSOI into production. The companies claim that FDSOI, despite more expensive engineered wafers as a starting point offers advantages in terms of scalability from low-voltage, low-power up to high performance.
The 12FDX process nominally at 12nm minimum geometry, is intended to enable the intelligent from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. It is notable that STMicroelectronics missed out on a design win with long time partner Mobileye that was attracted to 10nm FinFET (see Mobileye rejects FDSOI for EyeQ chip ).
The 12FDX process provides a step up in performance and avoids the need for triple- and quad-patterning and extreme ultraviolet lithography, said Rutger Wijburg, general manager of Globalfoundries' Dresden wafer fab where FDSOI is being developed. "If you look at performance with back-bias 22FDX is the same or better than 16/14nm FinFET process. With 12FDX with back bias you get better than 10nm FinFET processes," he told EE Times Europe .
In short 12FDX offers performance of 10nm FinFET with better power consumption and lower cost than 16nm FinFET.
"Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said Globalfoundries' CEO Sanjay Jha, in a statement. "Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems."
Customer tape-outs of 12FDX circuits are expected in the first half of 2019.
“NXP's next generation of i.MX multimedia applications processors are leveraging the benefits of FDSOI to achieve both leadership in power efficiency and scaling performance-on-demand for automotive, industrial and consumer applications,” said Ron Martino, vice president, i.MX applications processor product line at NXP Semiconductors. “Globalfoundries' 12FDX technology is a great addition to the industry because it provides a next generation node for FDSOI that will further extend planar device capability to deliver lower risk, wider dynamic range, and compelling cost-performance for smart, connected and secure systems of tomorrow."
Globalfoundries announcement was also welcomed in China.
"We are excited about the Globalfoundries 12FDX offering and the value it can provide to customers in China," said Xi Wang, Director General, Academician of Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology. "Extending the FDSOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products."
FDXcelerator
Alongside the announcement of 12FDX Globalfoundries announced the FDXcelerator program to ease migration to 22FDX from bulk nodes such as 40nm and 28nm planar CMOS.
Initial FDXcelerator Partners have committed to provide EDA tools that complement industry leading design flows by adding specific modules to easily leverage FDSOI body-bias differentiated features.
Features include basic, foundation and interface and complex IP. The partnership will also provide reference solutions, design consultation and services and product packaging and test solutions.
Initial partners are: Synopsys (EDA), Cadence (EDA), Invecas (IP and design solutions), Verisilicon (ASIC), CEA-Leti (services), and Encore Semiconductor (services).
I'm not sure GF is going to abandon FinFETS. 12FDX is probably going to be low-power stuff only.
The EyeQ5 is expected to be capable of more than 12 Tera operations per second, while keeping power consumption below 5W, to maintain passive cooling. Engineering samples of the EyeQ5 are expected to be available in the first half of 2018.