AMD Raven Ridge 'Zen APU' Thread

[itsmydamnation]

Well that's why I believe that AMDs SMT will be more like AMDs CMT and not like HT.
Sandy/ivy had HT on just 5 ports, zen has 10 that's too much even for HT makes sense though if you can cut up the core into two separate parts.

NO offence ( and by that i mean offence ) but what kind of crack are you smoking. AMD have already done a core architecture talk

Note the colour of the boxes and what they mean.

So How the hell is that CMT, what the F is CMT like? Here is a big clue for you, what are the differences between CMT and SMT?

Separate L1D, Separate Load and Store and separate integer ALU/AGU/PRF and retire. So where are the extra structures ELF? Remember we have a low rez die shot.

According To MR Kanter Skylake can only retire 4 ops per thread (while being able to issue 8) which is EXACTLY LIKE ZEN. Thats right AMD SMT is looking (at least at a high level) EXACTLY THE SAME AS SKYLAKE. Put down the crack pipe.

Zen = ALU, ALU, ALU, ALU, AGU, AGU, FPU, FPU, FPU, FPU (+3 VI ALUs but share the same exact units as FPUs, so -3)
SB = ALU, ALU, ALU, VI ALU, VI ALU, VI ALU, FPU, FPU, FPU, AGU, AGU, AGU (AVX is bridged so negating VI ALUs would also negate Zen's FPUs to only two FPUs; 8/9 mix versus 10/12 mix)

what the hell kind of crack is this? How many uops can i dispatch to execution units in a cycle. SB can issue 3 computational uops a cycle, if you count SB as 12 then i count Zen as 26 as it will take you 3 cycles to use all those units. Why aren't integer mul or div considered in your insane logic?


Profanity is not allowed in the technical forums,
Insulting other members is also not allowed.
Markfw
Anandtech Moderator

 

[NostaSeronx]

How many uops can i dispatch to execution units in a cycle. SB can issue 3 computational uops a cycle, if you count SB as 12 then i count Zen as 26 as it will take you 3 cycles to use all those units. Why aren't integer mul or div considered in your insane logic?

MUL/DIV are physically part of the units. They aren't separate nor can they be executed within the same bus. GPR / VI / FP utilize the same matrix port, but use different buses/units. Thus, can be executed exactly after the first op that went to another unit.

Zen is 10; 64-bit ALU, 64-bit ALU, 64-bit ALU, 64-bit ALU, AGU, AGU, 128-bit MUL, 128-bit ADD, 128-bit MUL, 128-bit ADD.
Sandy Bridge is 12; 64-bit ALU, 64-bit ALU, 64-bit ALU, Load AGU, Load AGU, Store Data, 128-bit VI ALU, 128-bit VI ALU, 128-bit VI ALU, 128-128(256-bit) FPU, 128-128(256-bit) FPU, 128-128(256-bit) FPU
SB = ALUs use GPR Units/Buses, VI ALUs use Integer AVX Units/Buses, FPU use FPU Units/Buses. 256-bit FPU AVX use two-ports of the matrix; VI ALU port(128-bit)((It goes to the FPU via bypass)) and FPU port(128-bit) to achieve a single AVX execution.

 

[otinane]

Is this for real ?

APU                  Raven Ridge FP5        Raven Ridge AM4
Socket                   FP5                        AM4
TDP                     4-35 W                   35-95W
CPU uArch                Zen                      Zen
Core/Thread              4/8                       4/8
GPU uArch                Vega                    Vega
GPU CUs                    12                        16
IMC                        DDR4                DDR4+HBM2
Process Node      14nm FinFET             14nm FinFET
Die Size              ~ 170 mm2           ~ 210 mm2

And arrival date 2H 2017?

 

[DrMrLordX]

Unknown.

 

[TimCh]

Is this for real ?

APU                  Raven Ridge FP5        Raven Ridge AM4
Socket                   FP5                        AM4
TDP                     4-35 W                   35-95W
CPU uArch                Zen                      Zen
Core/Thread              4/8                       4/8
GPU uArch                Vega                    Vega
GPU CUs                    12                        16
IMC                        DDR4                DDR4+HBM2
Process Node      14nm FinFET             14nm FinFET
Die Size              ~ 170 mm2           ~ 210 mm2

And arrival date 2H 2017?

H2 2017 is almost certain.

The 4 cores, 8 threads, 12 GPU CUs, DDR 4 version has been on a leaked road map slide from AMD. There are nothing solid about the HBM version, personally I doubt that it exists.

Sendt fra min SM-G928F med Tapatalk

 

[Tuna-Fish]

It's possible that Scorpio is a 4C8T Zen die plus a discrete Vega GPU. IOW more or less a PC.

Among other reasons that this is not true, there is no discrete 4C8T Zen die.

14nm masks are crazy expensive, and AMD opted to go for exactly two dies in the first year of Zen:

1: 8C16T dual channel DDR4 die without integrated graphics
2: 4C8T dual channel DDR4 die with integrated graphics.

All products are created by either cutting down those dies, or by combining multiple of them on a MCM.

 

[The Stilt]

Is this for real ?

No.

 

[Glo.]

Is this for real ?

APU                  Raven Ridge FP5        Raven Ridge AM4
Socket                   FP5                        AM4
TDP                     4-35 W                   35-95W
CPU uArch                Zen                      Zen
Core/Thread              4/8                       4/8
GPU uArch                Vega                    Vega
GPU CUs                    12                        16
IMC                        DDR4                DDR4+HBM2
Process Node      14nm FinFET             14nm FinFET
Die Size              ~ 170 mm2           ~ 210 mm2

And arrival date 2H 2017?

You should've provided the source for this: http://www.bitsandchips.it/english/...two-versions-of-raven-ridge-under-development

 

[otinane]

Well, of course i got that table from another site, but i didn't want to make it look like an advertisement or something. I' m not familiar with the forum policy.

Now on the subject, if they bring out an APU with HBM for desktop, i' m buying, else i keep rolling with my 5 year good old Phenom II x4.

 

[NTMBK]

Well, of course i got that table from another site, but i didn't want to make it look like an advertisement or something. I' m not familiar with the forum policy.

Typical procedure is to post a link back to the source, makes it easier to look into things further and get a feel for the context.

 

[sirmo]

Well, of course i got that table from another site, but i didn't want to make it look like an advertisement or something. I' m not familiar with the forum policy.

Now on the subject, if they bring out an APU with HBM for desktop, i' m buying, else i keep rolling with my 5 year good old Phenom II x4.

I don't know how much sense it makes to buy a $500+ HBM APU for the desktop, when it still won't compete with dGPUs and straight CPUs on the market. HBM APUs would be great for premium laptops and high density compute in the datacenter. HBM APUs won't be cheap.

 

[KTE]

I don't know how much sense it makes to buy a $500+ HBM APU for the desktop, when it still won't compete with dGPUs and straight CPUs on the market. HBM APUs would be great for premium laptops and high density compute in the datacenter. HBM APUs won't be cheap.

Initially, they won't be.

It also remains to be seen how much gain they provide vs the cost to implement, and where the gains becomr negligible.

Sent from HTC 10
(Opinions are own)

 

[deasd]

http://www.overclock.net/t/1619110/cpc-first-unofficial-ryzen-benchmarks/10#post_25730138

For Raven Ridge :

4C/8T
11CU, 704 units, 1.2GHz for ~ 2TFlops, around RX 460 level.

 

[prtskg]

For Raven Ridge :

4C/8T
11CU, 704 units, 1.2GHz for ~ 2TFlops, around RX 460 level.

That's high expectation for 2017 apu. May be this'll be true in 2018 with hbm but with ddr4, it's waste of silicon.

 

[dark zero]

That's high expectation for 2017 apu. May be this'll be true in 2018 with hbm but with ddr4, it's waste of silicon.

Not that high if they put HBM and premium price.
Even more, I see that comming since the RX 460 is already outdated.

 

[prtskg]

Not that high if they put HBM and premium price.
Even more, I see that comming since the RX 460 is already outdated.

HBM in 2017 seems unlikely, don't you think. Custom apu with HBM for Apple may be there as Apple will pay for it but I'm not so sure about general mass. I'd love it though.

 

[USER8000]

Unless AMD can find a way to give decent bandwidth to the GPU part of the APU,they are simply just making the chips more expensive to make.

 

[SpaceBeer]

They can't sell low end CPUs without IGP to compete with Celeron, Pentium and i3, so I'm sure we won't see APUs with HBM for 2 or 3 years, at least not in consumer market.

I supose first Raven Ridge APUs will come with IGPs with 6, 8 or 10 CUs

 

[USER8000]

They can't sell low end CPUs without IGP to compete with Celeron, Pentium and i3, so I'm sure we won't see APUs with HBM for 2 or 3 years, at least not in consumer market.

I supose first Raven Ridge APUs will come with IGPs with 6, 8 or 10 CUs

Maybe I needed to clarify my thoughts - I was meaning more that they should not plonk a huge GPU with the CPU if they cannot supply enough bandwidth. A smaller GPU which is more appropriate for the bandwidth that can be derived from DDR4 would make the CPU smaller,otherwise you will have a massive GPU sitting there doing nothing.

 

[prtskg]

Maybe I needed to clarify my thoughts - I was meaning more that they should not plonk a huge GPU with the CPU if they cannot supply enough bandwidth. A smaller GPU which is more appropriate for the bandwidth that can be derived from DDR4 would make the CPU smaller,otherwise you will have a massive GPU sitting there doing nothing.

This is exactly my thought. That's why I said without HBM or something similar, big gpu in apu will be waste of silicon.

 

[dark zero]

HBM in 2017 seems unlikely, don't you think. Custom apu with HBM for Apple may be there as Apple will pay for it but I'm not so sure about general mass. I'd love it though.

Actually there might be the bussiness who might pay for it.

However that would be on the similar range of the Broadwell C with better iGPU.

 

[The Stilt]

I cannot see many vendors, which would like to lock their systems to a fixed memory capacity. Outside Apple of course. Even with 12 - 14GB of the HBM reserved as system DRAM, that wouldn't be even close sufficient for professional workloads. And 16GB of HBM isn't exactly cheap.

 

[AtenRa]

That's high expectation for 2017 apu. May be this'll be true in 2018 with hbm but with ddr4, it's waste of silicon.

11CUs with Dual Channel DDR-4 3200MHz (~52GB/s) (for the Desktop) will be enough for 1080p gaming even for latest 2016 games at 1080p low/medium settings.

That is more than enough for this market, it will be more than 50% faster than any Intel iGPU in 2017/2018 at the same price point.

 

[SpaceBeer]

Cheap MBs (A320 and B350) officially suport DDR4 up to 2400MHz. Though I suppose we will see some benefits with 2666 or 2800MHz modules, similar like on FM2+. It will not be fast enough for latest AAA games, but for older ones (<= 2015) and all the indie games it will.

Regarding HBM, it could only make sense if it is used in a similar way as eDRAM in IrisPro, so both HBM (1-4GB) and RAM are needed. But I doubt it is possible to make such a chip for consumer segment at this moment. Maybe in 3-4 years from now

 

[AtenRa]

Intel Z170 officially supports up to 2133MHz DDR-4, we all know that Skylake IMC can work at higher clocks than DDR-4 3200.