Except that AMD's scale starts at 32CU with 1 HBM2 stack, and you can see that with Vega 10 and their exascale paper.The same as would be from 16C/32T+64CU+HBM2 chip. Its just scale you are touching with the designs.
It does not add up for me.
Server market, embedded and Machine Learning will get Horned Owl APU. And they would "EXTREMELY" benefit from 16 CU and HBM2 design, and would be great place where higher margin would play great role, apart from designs great efficiency.
Unless... all of the Raven Ridge APUs have HBM2.
Raven Ridge:
H2-2017 for notebooks
2018 for desktops
4 Zen cores + 11 CUs iGPU (Vega)
No HBM / HBM2
Pinnacle Ridge:
Zen cores (not Zen+ or Zen 2?)
Pinnacle Ridge sure is a nice way to say "Summit Ridge Refresh."
AMD's been copying Intel's marketing for years, it makes sense that they'd do a Kabylake
Hopefully it brings a nice clock speed boost with process improvements.
Links?Except that AMD's scale starts at 32CU with 1 HBM2 stack, and you can see that with Vega 10 and their exascale paper.
P. S. Curious enough their exascale paper seems to imply that Vega 10 is similar to Zeppelin in a sense of 2 smaller complexes glued together.
AMD started it, actually. Bristol Ridge came before Kaby Lake
Devils Canyon?AMD started it, actually. Bristol Ridge came before Kaby Lake
Devils Canyon?
Your slide does not disagree with my assessment that on AMD's scale you need at least 32 CUs for 1 HBM2 stack to be worth it, but does disagree with your guess that 4c+16 CU+1 HBM2 stack is a simple scale down from 16c+64 CU. Since you can't have 0.5 HBM2 stacks, can you?This is the design which we are talking about. Much simpler to manufacture. The GPU is monolithic. It has to be. There is not a single APU, both from Intel and AMD which have non-monolitihic design of the GPU.
Fairly positive Bristol uses same exact process as Carrizo. The only difference is that entire Carrizo die is finally functional.Devil's Canyon was called Haswell Refresh, there were no silicon changes, unlike Kaby and Bristol which had at least process improvements.
It does not work this way. And you perfectly know that, 1 Stack for 32 CUs is wrong. You are just trying to prove your point of view. Get better arguments, because you are better than this approach.Your slide does not disagree with my assessment that on AMD's scale you need at least 32 CUs for 1 HBM2 stack to be worth it, but does disagree with your guess that 4c+16 CU+1 HBM2 stack is a simple scale down from 16c+64 CU. Since you can't have 0.5 HBM2 stacks, can you?
Fairly positive Bristol uses same exact process as Carrizo. The only difference is that entire Carrizo die is finally functional.
And you perfectly know that, 1 Stack for 32 CUs is wrong
No, it is not. Also, Vega 10 is 64 CU with 2 HBM stacks and you perfectly know that too.AMD said:(one per GPU chiplet)
Since when is HBM2 latency is lower than DDR4? Even on memory controller as slow as Ryzen's. And if latency is not lower then it does not make sense as a cache.P.S. You forgot about most important thing in the APU topic. HBM2 memory is connected also to CPU, acting as L4 cache. HBM2 on APUs is not only about GPU. People on this very forum tend to forget about this fact.
I have literally been telling you and everyone on this forum for years that an HBM2 consumer APU isn't happening for a long time, HBM2 is so expensive that it would be literally unusable by the vast majority of OEMs/designs.
Is Vega chiplet Based GPU? Is Greenland Chiplet based design?No, it is not. Also, Vega 10 is 64 CU with 2 HBM stacks and you perfectly know that too.
Since when is HBM2 latency is lower than DDR4? Even on memory controller as slow as Ryzen's. And if latency is not lower then it does not make sense as a cache.
What if i say that Vega is a chiplet based GPU? For all we know it is basically 2 GPU chiplets.Is Vega chiplet Based GPU? Is Greenland Chiplet based design?
For very simple reason. AMD lifted the 4 Shader Engine requirement for the monolithic GPU designs. If what you are saying is true, 64 CU design would be made from 2 Chiplets made from 32 CU, each, with 4 Shader Engines, each and whole idea about Shader Engine limit would be pointless.What if i say that Vega is a chiplet based GPU? For all we know it is basically 2 GPU chiplets.
Greenland is definitely chiplet based design, considering it uses CPU chiplets (aka Zen CCXs).
Even going with your assumption on the expense of HBM2, when you consider the potential server APU market, then AMD are likely to do the design.
After which, producing a variant for companies wanting a high-end ultrabook with strong cpu+graphics and strong battery life in the one package (albeit, not simultaneously), then a consumer variant is not just possible, but very likely.
Is Vega chiplet Based GPU? Is Greenland Chiplet based design?
No. Navi is.
Two things about latency, which you completely forgot. Infinity Fabric, and HBCC.
What we know about Vega architecture: 64 CUs, 2 stacks of HBM2, no serious changes apart from support for vec2 fp16 and ever larger geometry throughput. What else?You have been confused by the prototypes, and not been paying attention to what we know already about Vega architecture. It is monolithic design. There are no chiplets, apart from MCM Snowy Owl package, maybe.
Well, scalability has to mean something. And we know AMD is pushing for MGPU support, and the industry is headed in the direction of chiplets...Sweet, you have details about Navi? Please share, preferably with sources
Did you even read the preview?What we know about Vega architecture: 64 CUs, 2 stacks of HBM2, no serious changes apart from support for vec2 fp16 and ever larger geometry throughput. What else?
Well, scalability has to mean something. And we know AMD is pushing for MGPU support, and the industry is headed in the direction of chiplets...
There is no clear cut evidence for Navi being made of chiplets, but there's a good chance.
Seriously this is all you were able to get from what AMD presented? How can you show this level of incompetence, and then discuss technology on forums?What we know about Vega architecture: 64 CUs, 2 stacks of HBM2, no serious changes apart from support for vec2 fp16 and ever larger geometry throughput. What else?
Nope. First "glimpse" of scalability we will see with Vega. We have this info today about Raven Ridge APU. 4C/8T+11 CU design. We know that Raven Ridge uses Vega architecture. High Bandwidth Cache Controller is inherent part of Vega architecture, and will be available regardless if the APU will have HBM2 on the package, or not.Here's what I think scalability means.
Polaris only covers the low end/mid range of the market, Vega only the high end/enthusiast part of the market. Navi might simply be a broader family of chips designed to span both the markets that Polaris and Vega will, together, cover.
That would be odd. Nothing architectural about Vega would prevent it from scaling down as far as I can tell.Here's what I think scalability means.
Polaris only covers the low end/mid range of the market, Vega only the high end/enthusiast part of the market. Navi might simply be a broader family of chips designed to span both the markets that Polaris and Vega will, together, cover.
There are so many problems with what you just stated I don't even know where to begin.What this means is that for example, if you have Raven Ridge APU in your computer, and you buy Vega 11 GPU, with 48 CUs, and HBM2, the APU will still have direct access to the HBM2 on Vega dGPU, so total CU, with full performance available to your system will be 59 CUs and direct access to the HBM2. Navi will only increase the scalability capabilities.