AMD Raven Ridge 'Zen APU' Thread

[Glo.]

There are so many problems with what you just stated I don't even know where to begin.
Infinity Fabric isn't magic, it can't bypass the PCI-E if the card is in the PCI-E slot and the APU is in the CPU socket. It will be limited to PCI-E bandwidth. So I have no idea how you intend the APU to use Vega 11's HBM2, and how it would be better than just accessing system RAM.

And that's without even going about communication between two GPU's for rendering, let alone GPU's in two entirely different classes of performance.

Why do you think I do not know this? The thing about memory syncing is invalid. Vega has on hardware level Unified Memory.

I don't know how this works "exactly" but this is what I understood from discussions with people who actually understand hardware way better than I do. They even indicated that this feature looks to be specifically designed for use cases, in Laptops and External GPUs... So you are getting bottlenecked on the bandwidth front even more, than PCIe socket. But this appears to be the case.

 

[tamz_msc]

How big is the HBCC? This is the most important question that will determine if Vega can be scaled down to fit in an APU.

Otherwise it would seem that the HBCC is exclusive to 500$+ dGPUs, which wouldn't solve the memory bandwidth issues which are relevant in the case of integrated graphics.

 

[CatMerc]

How big is the HBCC? This is the most important question that will determine if Vega can be scaled down to fit in an APU.

Otherwise it would seem that the HBCC is exclusive to 500$+ dGPUs, which wouldn't solve the memory bandwidth issues which are relevant in the case of integrated graphics.

Raven Ridge will be Vega based. So we know it can be scaled down.

 

[tamz_msc]

Raven Ridge will be Vega based. So we know it can be scaled down.

That doesn't mean that the HBCC is going to make it unless there are no size constraints. I know this is not the right comparison but the EDRAM controller on Crystalwell which was on the CPU die took up as much space as two cores.

 

[Glo.]

That doesn't mean that the HBCC is going to make it unless there are no size constraints. I know this is not the right comparison but the EDRAM controller on Crystalwell which was on the CPU die took up as much space as two cores.

There is no point of Vega architecture if there is no HBCC on the die. They could've just used Polaris, instead.

 

[tamz_msc]

There is no point of Vega architecture if there is no HBCC on the die. They could've just used Polaris, instead.

I agree with you that the HBCC is perhaps the most important feature of Vega, but we don't know how big it is in relation to the rest of the stuff in the GPU die.

 

[lobz]

AMD started it, actually. Bristol Ridge came before Kaby Lake

god, not this nonsese again, please... Bristol ridge brought (a mucu needed) ddr4 and a completely new, multi-year platform. Please compare this to kaby lake again, if you must, but don't use that winky-smiley, it just makes you seem clueless, which you are clearly not!

 

[lolfail9001]

Seriously this is all you were able to get from what AMD presented? How can you show this level of incompetence, and then discuss technology on forums?

Polaris history has to forced me to be highly suspect of everything AMD touts in previews and seek answers in what their past uarches presented. Study their presentation attentively and look at past GCN uarches for answers.

Did you even read the preview?
I would argue Vega is nearly as large as the move from VLIW to GCN.

Yes, i have read the preview. Then i have read Polaris preview, compared it to actual Polaris review, and applied same salt to Vega preview. Product of said research: Vega is Fiji 2.

Vega architecture is NOT 64 CUs. GPU that is using Vega architecture is made from 64 CU design plus 2048 bit memory controller, and 8 GB of HBM2.

GPU that is using Vega architecture is called Vega, in case you have forgot.

High Bandwidth Cache Controller is inherent part of Vega architecture, and will be available regardless if the APU will have HBM2 on the package, or not.

HBCC is only relevant if you have VRAM but not enough of it, it is extension of Fiji's "dynamic memory" workaround for 4GB of HBM1. On APU without HBM or some other sort of memory buffer it is utterly useless.

What this means is that for example, if you have Raven Ridge APU in your computer, and you buy Vega 11 GPU, with 48 CUs, and HBM2, the APU will still have direct access to the HBM2 on Vega dGPU, so total CU, with full performance available to your system will be 59 CUs and direct access to the HBM2.

Except that system memory is faster than PCI-E bus so it won't work in any capacity.

Raven Ridge will be Vega based. So we know it can be scaled down.

I do think RR CUs will use Gfx IP 9 and other Vega stuff, but it is almost certainly not Vega 10 based. (and we do not know anything about any other Vega GPU), in fact, i do not even remember hints of it except ROCm roadmap.

god, not this nonsese again, please... Bristol ridge brought (a mucu needed) ddr4 and a completely new, multi-year platform. Please compare this to kaby lake again, if you must, but don't use that winky-smiley, it just makes you seem clueless, which you are clearly not!

AMD could have done it with Carrizo but decided against it, that's it. Also, that "completely new, multi-year" platform only came to us with Ryzen and it was still half-baked. Bristol Ridge is the same OEM pipeline filler Kaby Lake is, seriously.

 

[tamz_msc]

Yes, i have read the preview. Then i have read Polaris preview, compared it to actual Polaris review, and applied same salt to Vega preview. Product of said research: Vega is Fiji 2.

Yeah and Maxwell is Kepler 2 because it only adds tiled rendering and memory compression.

HBCC is only relevant if you have VRAM but not enough of it, it is extension of Fiji's "dynamic memory" workaround for 4GB of HBM1. On APU without HBM or some other sort of memory buffer it is utterly useless.

Are we forgetting this?

 

[lobz]

Polaris history has to forced me to be highly suspect of everything AMD touts in previews and seek answers in what their past uarches presented. Study their presentation attentively and look at past GCN uarches for answers.

Yes, i have read the preview. Then i have read Polaris preview, compared it to actual Polaris review, and applied same salt to Vega preview. Product of said research: Vega is Fiji 2.

GPU that is using Vega architecture is called Vega, in case you have forgot.

HBCC is only relevant if you have VRAM but not enough of it, it is extension of Fiji's "dynamic memory" workaround for 4GB of HBM1. On APU without HBM or some other sort of memory buffer it is utterly useless.

Except that system memory is faster than PCI-E bus so it won't work in any capacity.

I do think RR CUs will use Gfx IP 9 and other Vega stuff, but it is almost certainly not Vega 10 based. (and we do not know anything about any other Vega GPU), in fact, i do not even remember hints of it except ROCm roadmap.

AMD could have done it with Carrizo but decided against it, that's it. Also, that "completely new, multi-year" platform only came to us with Ryzen and it was still half-baked. Bristol Ridge is the same OEM pipeline filler Kaby Lake is, seriously.

of course, whatever it takes to bend facts into subjective perceptions, seriously

 

[Glo.]

Polaris history has to forced me to be highly suspect of everything AMD touts in previews and seek answers in what their past uarches presented. Study their presentation attentively and look at past GCN uarches for answers.

It has nothing to do with marketing, it has everything to do with understanding the technology, and the nature of the chip itself. Secondly, everything what AMD have shown in press release, about the high-level changes have appeared in the actual chip. Primitive Discard Accelerator, increased cache sizes, etc.

Yes, i have read the preview. Then i have read Polaris preview, compared it to actual Polaris review, and applied same salt to Vega preview. Product of said research: Vega is Fiji 2.

Nope. You did not understood what you have been reading. At all.

HBCC is only relevant if you have VRAM but not enough of it, it is extension of Fiji's "dynamic memory" workaround for 4GB of HBM1. On APU without HBM or some other sort of memory buffer it is utterly useless.

This is misinformation spread by you based on your not understanding the nature of technology. Look at it from broader point of view, not only GPUs. Not only gaming.

 

[CatMerc]

Polaris history has to forced me to be highly suspect of everything AMD touts in previews and seek answers in what their past uarches presented. Study their presentation attentively and look at past GCN uarches for answers.

Yes, i have read the preview. Then i have read Polaris preview, compared it to actual Polaris review, and applied same salt to Vega preview. Product of said research: Vega is Fiji 2.

Umm, I don't see a problem here?
Polaris delivered on what it promised, with the exception of power efficiency (which could be easily attributed to various number skewing methods like using golden chips, or using TDP's instead of actual power consumption). Where people took things too far is where the promises were more generic. Better L2 cache, better command processor, etc' etc'. It's there, people just took what it means way too far. In the end it's just refined GCN. It's even ISA compatible with Fiji.

With Vega, there are multiple very specific improvements that should bring major uplifts in performance or efficiency. Tile based rasterization chiefly among them, large improvements to geometry throughput - a historic weak point for GCN compared to NVIDIA, higher clockspeeds, HBCC (which is fairly huge when you consider how expensive HBM2 is), etc'.
These all target areas where NVIDIA is ahead of AMD, hopefully bridging any architectural gap that has built up while the GPU division was starved for resources that went to Zen.

Don't get me wrong - I still have major doubts about Vega. If it really is a 540mm^2 die and all it does is 1080 performance + 10%, then this is a disaster. But to claim it's just Polaris with packed math and geometry improvements would be silly.

 

[lolfail9001]

Yeah and Maxwell is Kepler 2 because it only adds tiled rendering and memory compression.

http://www.anandtech.com/show/7764/the-nvidia-geforce-gtx-750-ti-and-gtx-750-review-maxwell/2

You know, you got me to reread 750 ti articles, and i just had to chuckle a little when i have seen this.

Are we forgetting this?

Does not affect relevancy of HBCC on a GPU without dedicated VRAM buffer.

It has nothing to do with marketing, it has everything to do with understanding the technology, and the nature of the chip itself. Secondly, everything what AMD have shown in press release, about the high-level changes have appeared in the actual chip. Primitive Discard Accelerator, increased cache sizes, etc.

Yes, and compare what happened to what was hyped about generic things like "new" Command processor and stuff. HBCC is one of those generic things that we know no real technical details of except that it affects performance in VRAM volume limited situations and allows stuff like SSG to be usable. Fiji much? "Improved load balancing" will probably be the same story, where simply faster geometry processing suddenly affords the rest of GPU to breathe freely.

Umm, I don't see a problem here?

Neither do i, i do believe that Vega will have easily have 2x faster geometry throughput per clock compared to Fiji and will support vec2 fp16 in full. But that's the only 2 of 3 exact technical things (third being DSB rasterizer with RoPs becoming clients of L2) we know about architecture so far, don't we? HBCC is generic, higher clockspeeds is generic, higher "IPC" is generic too.

Nope. You did not understood what you have been reading. At all.

Oh, i did all too well, what i took away from it is to look at what AMD has done on previous revisions of GCN and turn it to 11. Take Tonga, turn it to 11, add AVFS from Carrizo and you produce Polaris 10, that's how it works.

This is misinformation spread by you based on your not understanding the nature of technology. Look at it from broader point of view, not only GPUs. Not only gaming.

I do, and it still looks like everything AMD has shown with Fiji to work around it's unfortunate memory limitation.

 

[CatMerc]

Neither do i, i do believe that Vega will have easily have 2x faster geometry throughput per clock compared to Fiji and will support vec2 fp16 in full. But that's the only 2 of 3 exact technical things (third being DSB rasterizer with RoPs becoming clients of L2) we know about architecture so far, don't we? HBCC is generic, higher clockspeeds is generic, higher "IPC" is generic too.

Could you remind me what DSB stands for? It escaped my head completely

I agree, higher IPC is generic.
HBCC is generic though we've seen its effects in action in a side by side comparison, something we can't say for the generic Polaris improvements.
Wouldn't call higher clockspeeds generic, since it can't mean anything other than... you know, higher clockspeeds. And we know what clockspeed does, don't we?

TBR, ROPs being clients of L2, increased geometry throughput, and clockspeed uplift should by themselves account for major performance or efficiency improvements. Packed FP16 math too when used. I'd say it's already enough to say that Vega is a major major step forward, as long as execution doesn't go down the toilet.

 

[tamz_msc]

You know, you got me to reread 750 ti articles, and i just had to chuckle a little when i have seen this.

I should have said Maxwell 2nd Gen., but my point still stands. Or do you believe that inclusion of the biggest features that gives NVIDIA its efficiency lead does not warrant a new name for the architecture.

Does not affect relevancy of HBCC on a GPU without dedicated VRAM buffer.

How do you expect the VRAM limit to be addressed in the future, may I ask? By adding even more GDDR5X/6 chips?
Just because HBCC was demoed at an intentionally crippled 2GB doesn't mean that memory limitations aren't there even if you have 11/12GB of VRAM.

 

[tamz_msc]

Could you remind me what DSB stands for? It escaped my head completely

Draw Stream Binning Rasterizer aka. tiled rendering.

 

[CatMerc]

Draw Stream Binning Rasterizer aka. tiled rendering.

Ah yes, AMD and their special cookie names.

 

[imported_jjj]

If you look at Polaris as FLOPS per W and you factor in the wider memory bus, Polaris is very competitive.
Gaming is a bit of a problem lol and Zen's gaming "problems" make this extra funny.

The fact that Nvidia has launched the 1080 TI at 700$, tells us where Vega is - without great precision but Nvidia does such preemptive moves often and this was such a move.
Vega should beat it in efficiency, HBM is enough for that. How close perf is, hard to say ,if it's very close, AMD is still some 10% behind in utilization.

 

[lolfail9001]

How do you expect the VRAM limit to be addressed in the future, may I ask? By adding even more GDDR5X/6 chips?

I do not think VRAM limit is even relevant outside of compute scenarios (i mean, seriously, nV had to reference WD2 at 5k to get the VRAM limitation point across, who wants to check how a single 1080Ti does at 5k ultra in WD2?). Also i do not expect GDDR5X/GDDR6 ICs to sit at 8Gigabit forever .

I should have said Maxwell 2nd Gen., but my point still stands. Or do you believe that inclusion of the biggest features that gives NVIDIA its efficiency lead does not warrant a new name for the architecture.

Sure, they can use new names all they like and it sure sounds much more justified than pretending Polaris was a big architecture rework.

Wouldn't call higher clockspeeds generic, since it can't mean anything other than... you know, higher clockspeeds. And we know what clockspeed does, don't we?

For all we know it means they are clocked 70Mhz higher than rx480 in stock

 

[tamz_msc]

I do not think VRAM limit is even relevant outside of compute scenarios (i mean, seriously, nV had to reference WD2 at 5k to get the VRAM limitation point across, who wants to check how a single 1080Ti does at 5k ultra in WD2?). Also i do not expect GDDR5X/GDDR6 ICs to sit at 8Gigabit forever.

Where are the GDDR5X modules with >8Gb capacity? I can make the same argument to say that HBM2 won't sit at 8Gb/stack or be expensive to manufacture forever?

Sure, they can use new names all they like and it sure sounds much more justified than pretending Polaris was a big architecture rework.

So Maxwell 2 is an architecture rework, while Polaris isn't?

 

[lolfail9001]

I can make the same argument to say that HBM2 won't sit at 8Gb/stack or be expensive to manufacture forever?

But your argument is not in favor of HBCC as concept to compensate for lack of VRAM.

So Maxwell 2 is an architecture rework, while Polaris isn't?

See that slide with all "new" blocks? That slide is the reason why i am so skeptical about Vega.

 

[Glo.]

L2 cache - 4 times bigger in Polaris than it is on previous versions of GCN.
Display Engine - completely new, and updated to latest standards.

The ONLY thing that is not exactly understandable is why there is "NEW" close to Memory Controller. Unless it is 100% compatible with GDDR5X - it would not require to be new. There is no need for new memory controller, even if you are using faster GDDR5 memory(look at GTX 1060 8000 vs 9000 MHz memory, right now). So it is... strange. But who knows? Maybe upcoming RX 580's are going to use GDDR5X?

 

[JDG1980]

The ONLY thing that is not exactly understandable is why there is "NEW" close to Memory Controller. Unless it is 100% compatible with GDDR5X - it would not require to be new. There is no need for new memory controller, even if you are using faster GDDR5 memory(look at GTX 1060 8000 vs 9000 MHz memory, right now). So it is... strange. But who knows? Maybe upcoming RX 580's are going to use GDDR5X?

The pre-Polaris GCN memory controller just wasn't that good. It topped out between 1400 and 1750 MHz, with Bonaire having the best memory speeds and Pitcairn the worst. To be able to use a 256-bit memory bus on Polaris 10 without throttling the card, it had to be redesigned.

I believe it does support GDDR5X but that doesn't mean we will necessarily get it in a shipping product. Tonga silicon supported a 384-bit memory bus, but that was never shipped.

 

[JDG1980]

Pinnacle Ridge sure is a nice way to say "Summit Ridge Refresh."

That is not clear from the slides. Does "Zen" refer to just the first iteration of the architecture, or the entire family?

We don't have enough information yet to say if "Pinnacle Ridge" is just renamed Summit Ridge (along the lines of Kaveri->Godavari or Haswell->Devils Canyon) or if it is actually a real successor to Summit Ridge with bugfixes, optimizations, etc. It's perhaps noteworthy that Mark Papermaster said that Zen would be iterated - "tock, tock, tock, tock". Apparently there are bugs and weak points in the existing Ryzen chips that have already been fixed, but didn't make it in time for the cutoff for the first release.

 

[lolfail9001]

L2 caclhe - 4 times bigger in Polaris than it is on previous versions of GCN.

Not exactly impactful, however.

Display Engine - completely new, and updated to latest standards.

Completely new said who? From my perspective and perspective of AMD's own driver it looks like updated display IP of Carrizo.

The ONLY thing that is not exactly understandable is why there is "NEW" close to Memory Controller. Unless it is 100% compatible with GDDR5X - it would not require to be new. There is no need for new memory controller, even if you are using faster GDDR5 memory(look at GTX 1060 8000 vs 9000 MHz memory, right now). So it is... strange. But who knows? Maybe upcoming RX 580's are going to use GDDR5X?

See: Ryzen memory controller woes.