I still haven't seen a single thing from anyone that indicates to me that AMD has bothered to use a different die floor plan for Raven Ridge from the Horned Owl SoC. The Horned Owl SoC, from AMD's own official slide, has listed an 8MB L3 cache. Given how resource constrained AMD is, it would be financially irresponsible to make a completely different die for Horned Owl and Raven Ridge where they will only really differ in packaging and perhaps some micro-code revisioning. Where they might, and I mean MIGHT decide to use a different die is in the smaller, more cut down Soc family under Horned Owl. It's got 2 cores, half the Gcn cores, and half the L3 listed. With all of that disabled, is it more economical to use recovered Raven Ridge dies (assumes high failure rate) or is it more economical to make a half sized SoC die (could generate over twice as many per wafer, making running cost basis much lower while still meeting the needs of the SoC world well enough). I think that a full dress desktop Raven Ridge part will be made, it will have 8MB of L3, and probably clock as high as AMD can manage. In a tiny, well designed case, it would be a great home theater/STB part that gives enough performance for lots of casual gamers. Priced reasonably, I'd jump on one in a heartbeat for my living room.