AMD Raven Ridge 'Zen APU' Thread

[Dresdenboy]

Define VEGA IP. Does that mean VEGA GPU or an enhanced Polaris?

Looks like you are actually asking about HBM. Vega is not only that (could even work without the HBCC or some other memory as HBC I think), but NCU, primitive rasterizers, etc.

 

[bjt2]

What does this mean?

Nothing... It was a joke... My point is that a new APU can't have one year old technology. Vega is already finalized, why they would use an old design for the GPU? And i doubt that Polaris has infinity fabric. It will be a pity have an old design without infinity fabric glued to a new design with infinity fabric. How do you glue it? Onion and Garlic buses does not exist anymore...
EDIT: and polaris has GDDR5 controller, i doubt it have also HBM...

 

[Phynaz]

Looks like you are actually asking about HBM. Vega is not only that (could even work without the HBCC or some other memory as HBC I think), but NCU, primitive rasterizers, etc.

Yep, and that's what I'm asking, what does Vega IP mean? Put a Vega rasterizer block on a Polaris GPU and now the APU has "Vega IP". But that doesn't make it a Vega GPU.

If it's a Vega GPU then why didn't his AMD rep says it's a Vega GPU?

We just have to await his response.

 

[Glo.]

Yep, and that's what I'm asking, what does Vega IP mean? Put a Vega rasterizer block on a Polaris GPU and now the APU has "Vega IP". But that doesn't make it a Vega GPU.

If it's a Vega GPU then why didn't his AMD rep says it's a Vega GPU?

We just have to await his response.

Tonga is Graphics IPv8, Fiji is Graphics IPv8.1, and Polaris is Graphics IPv8.2.
Vega is Graphics IPv9.

I have absolutely no idea where you get the thought that such different IP family can be enhanced Polaris GPU. Connect the dots. You do not need words from rep to get conclusions.

Vega is too different architecture. It is not compatible with previous versions of GCN without layer of abstraction. You cannot just take out Rasterization block and put it in Polaris, and call it Vega. It will simply be Polaris GPU with enhanced rasterization. Nothing more. Remember that in Vega everything is connected to L2 cache, rather than memory controller, like it was with previous versions of GCN.

 

[Doom2pro]

Some Engineering Samples have surfaced, some think they might be Raven Ridge?

AMD Eng Sample: 2M3001C3T4MF2_33/30_N with AMD 15DD iGPU
AMD Eng Sample: ZD3101AHM44AB_38/31/13/07_9874 with Radeon R7

Source: https://videocardz.com/65654/amd-ryzen-6-core-cpu-exists (Comment Section)

 

[Dresdenboy]

Some Engineering Samples have surfaced, some think they might be Raven Ridge?

AMD Eng Sample: 2M3001C3T4MF2_33/30_N with AMD 15DD iGPU
AMD Eng Sample: ZD3101AHM44AB_38/31/13/07_9874 with Radeon R7

Source: https://videocardz.com/65654/amd-ryzen-6-core-cpu-exists (Comment Section)

Thanks, nice find!

The first string has the typical "_N" ending, a "F2" stepping ID (could be B0) close to the already seen "F3". But "M" for the cache configuration is new to me. The last known 4C string from Zauba was "2D2802AUM4KE4" with a "K" for the cache.

The second mobile ES seems to be some CZ variant (or BR?) -> Device ID 9874.

 

[Glo.]

Thanks, nice find!

The first string has the typical "_N" ending, a "F2" stepping ID (could be B0) close to the already seen "F3". But "M" for the cache configuration is new to me. The last known 4C string from Zauba was "2D2802AUM4KE4" with a "K" for the cache.

The second mobile ES seems to be some CZ variant (or BR?) -> Device ID 9874.

Yes, the second one is Bristol Ridge, and it was easy to deduct: 44 - 4 Core, 4 Thread, 3100 MHz base, 3800 Boost, just like one of 35W Bristol Ridge SKUs. A12-9800E, to be precise.

About The first one. I though that all numbers indicate the core clocks of the hardware: 33/30 is the core clock of the CPU, but 15 can indicate... core clock of the GPU.

 

[Glo.]

AMD Eng Sample: 2M3001C3T4MF2_33/30_N with AMD 15DD iGPU

ES1, Mobile unit, 3.0 GHz Base clock, 1st revision, C3 - possibly lower than 65W TDP, most likely 35W(!), package ?, 4 cores, different cache(2MB L2 + 8 MB L3 + HBM2 L4?)

Nobody expected that 8 core CPU can be locked to 65W TDP. So there still can be massive surprises with Raven Ridge APUs.

 

[CatMerc]

Thanks, nice find!

The first string has the typical "_N" ending, a "F2" stepping ID (could be B0) close to the already seen "F3". But "M" for the cache configuration is new to me. The last known 4C string from Zauba was "2D2802AUM4KE4" with a "K" for the cache.

The second mobile ES seems to be some CZ variant (or BR?) -> Device ID 9874.

I imagine Raven Ridge's cache configuration is different from the previous known 4C's because of Vega's cache.
I would not be surprised at all if it has its own L3 cache to help with bandwidth issues.

Edit: Posted this in a Ryzen thread, might as well post this in a Raven thread

Spoiler: Large Image Ahead

This is Summit Ridge -4C with 11 CU's and 8 ROP's based on a die shot of RX 480.

 

[otinane]

From leaks so far, it seems they will also release a server APU (Snowy Owl) as well to the mobile APU, and the desktop APU (Raven Ridge).

I 'm having trouble to find a real world case scenario of a group of consumers who would choose a server APU over a server CPU (Napples) and/or a Pro series GPU.

I mean what's the point to spend extra money for a server motherboard etc just to use something that will perform much less than of the real deal.

 

[jpiniero]

I 'm having trouble to find a real world case scenario of a group of consumers who would choose a server APU over a server CPU (Napples) and/or a Pro series GPU.

Snowy Owl is for compute only really; The latency between the CPUs and the GPU(s?) would be much lower than PCIe.

 

[otinane]

I thought CPU is used for linear calculations, and GPU for parallel.

So an APU can be used as both, with the specific software instructions?

 

[DrMrLordX]

GPU is good for highly-parallelized computations where bus latency is not going to be an issue. iGPU helps to minimize bus latency problems, opening up GPGPU to some areas where it would otherwise be impractical.

 

[hojnikb]

Any leaks yet on ultra low power parts ?

 

[casiofx]

It would be awesome if AMD could make a soldered CPU/MOBO with:
1) Zen 8 cores + polaris 2304sp + 16GB shared HMB2 in a single package, and 200 watts air cooler.
2) secondary upgradable ddr4 ram slots.

It would be such a small but awesome pc

 

[otinane]

GPU is good for highly-parallelized computations where bus latency is not going to be an issue. iGPU helps to minimize bus latency problems, opening up GPGPU to some areas where it would otherwise be impractical.

So actually, if we think this following scenario, with me for example getting an APU and discrete GPU.

I force through BIOS the video (parallel computation) going to the discrete GPU. The GPU cores inside the APU they aren't disabled just remain inactive.

If then i have data (no video) that require parallel computation and/or serial, with the proper software the cpu and gpu cores work together correct?

 

[Glo.]

So actually, if we think this following scenario, with me for example getting an APU and discrete GPU.

I force through BIOS the video (parallel computation) going to the discrete GPU. The GPU cores inside the APU they aren't disabled just remain inactive.

If then i have data (no video) that require parallel computation and/or serial, with the proper software the cpu and gpu cores work together correct?

If you have Vega GPU and Raven Ridge APU - you do not need to do anything. Because of the exactly the same natyure of architectures used in the hardware, and the HBCC in the APU, you will get access to HBM2 from the GPU. There will be perfect expansion of Vega GPU, regardless if it is Vega 11 or Vega 10. You do not need in this setup to have HBM2 on APU.

In other words, lets say you buy 4C/8T APU with 16 CU's but without HBM2, and you get also Vega 11 with 48 CU's. Total amount of CUs seen by the system is 64. And all of them have access to HBM2.

If you have only APU in your computer - you better go for the ones with HBM2.

 

[otinane]

I see that explains a lot, and saves me one step from my final target.

Do all CU taking part in calculations of a batch of data, or this is something that has to do with the nature of the data?Can i trick an APU to use both CPU and GPU cores for computing?

If yes, this is on the software side, and how it communicates the data to the APU, or the APU's instructions set?

 

[Sweepr]

Raven Ridge:
H2-2017 for notebooks
2018 for desktops
4 Zen cores + 11 CUs iGPU (Vega)
No HBM / HBM2

Pinnacle Ridge:
Zen cores (not Zen+ or Zen 2?)

 

[imported_jjj]

So as expected,mobile first and 11CUs for RR.

 

[Topweasel]

I imagine Raven Ridge's cache configuration is different from the previous known 4C's because of Vega's cache.
I would not be surprised at all if it has its own L3 cache to help with bandwidth issues.

Edit: Posted this in a Ryzen thread, might as well post this in a Raven thread
This is Summit Ridge -4C with 11 CU's and 8 ROP's based on a die shot of RX 480.

It should the L3 cache is baked inside the ccx module. The wouldn't go to the trouble of developing this scalable module, and then have to change it immediately for one of their product lines.

 

[Glo.]

It does not add up for me.

Server market, embedded and Machine Learning will get Horned Owl APU. And they would "EXTREMELY" benefit from 16 CU and HBM2 design, and would be great place where higher margin would play great role, apart from designs great efficiency.

Unless... all of the Raven Ridge APUs have HBM2.

 

[lolfail9001]

Server market, embedded and Machine Learning will get Horned Owl APU. And they would "EXTREMELY" benefit from 16 CU and HBM2 design, and would be great place where higher margin would play great role, apart from designs great efficiency.

What "extreme" benefit there would be for server market or machine learning from 16 CU APU? I mean, come on, quad socket server with computing power of a single GPU workstation? Hell, due to needless parts being duplicated it would be even less efficient than single GPU workstation.

 

[Glo.]

What "extreme" benefit there would be for server market or machine learning from 16 CU APU? I mean, come on, quad socket server with computing power of a single GPU workstation? Hell, due to needless parts being duplicated it would be even less efficient than single GPU workstation.

The same as would be from 16C/32T+64CU+HBM2 chip. Its just scale you are touching with the designs.

 

[Atari2600]

Server market, embedded and Machine Learning will get Horned Owl APU.

Is Horned Owl linked to Snowy Owl?

I'd assumed Snowy Owl would be the first iteration of the Server APU...?

[But I've seen folks say Snowy Owl is a completely separate, GPU-less server --- I don't really see what distinguishes it from Naples though.]