Completely new said who? From my perspective and perspective of AMD's own driver it looks like updated display IP of Carrizo.
Polaris has support for DisplayPort 1.3, which Carrizo lacks.
Completely new said who? From my perspective and perspective of AMD's own driver it looks like updated display IP of Carrizo.
That's why i said updated, it is definitely not renamed GCN1.2 display controller.Polaris has support for DisplayPort 1.3, which Carrizo lacks.
Just how many GDDR5X/6 modules can you keep adding on a PCB before you are going to ask yourself whether this is the right approach? The Jeffery Cheng Q/A video should give you a clue what HBCC is about.But your argument is not in favor of HBCC as concept to compensate for lack of VRAM.
That's a reflection of the semi-custom aspect of RTG.See that slide with all "new" blocks? That slide is the reason why i am so skeptical about Vega.
It is one CCX , Raven Ridge is a native quad core + iGPU die. We don't know if it will have an L3 cache, I suppose it will.Any indication of whether the 4 Zen cores of Raven Ridge comprise 1 or 2 CCX, like Ryzen 5?
Polaris does support GDDR5X.L2 cache - 4 times bigger in Polaris than it is on previous versions of GCN.
Display Engine - completely new, and updated to latest standards.
The ONLY thing that is not exactly understandable is why there is "NEW" close to Memory Controller. Unless it is 100% compatible with GDDR5X - it would not require to be new. There is no need for new memory controller, even if you are using faster GDDR5 memory(look at GTX 1060 8000 vs 9000 MHz memory, right now). So it is... strange. But who knows? Maybe upcoming RX 580's are going to use GDDR5X?
Any links that are confirming this? Im not saying it is not, but, I would like to see confirmation.Polaris does support GDDR5X.
Can't find it, it was in some AMA or interview during the Polaris release time. When questioned about the IMC, they stated it's capable of supporting GDDR5X should they find a need for it.Any links that are confirming this? Im not saying it is not, but, I would like to see confirmation.
Agree. Extrapolating from inargualble biz logic empathetically, reveals much IMO.Nothing... It was a joke... My point is that a new APU can't have one year old technology. Vega is already finalized, why they would use an old design for the GPU? And i doubt that Polaris has infinity fabric. It will be a pity have an old design without infinity fabric glued to a new design with infinity fabric. How do you glue it? Onion and Garlic buses does not exist anymore...
EDIT: and polaris has GDDR5 controller, i doubt it have also HBM...
It is one CCX , Raven Ridge is a native quad core + iGPU die. We don't know if it will have an L3 cache, I suppose it will.
It will. It's embedded into the design of the CCX. We really need to start looking at the CCX like we did the BD module.
I agree It defies logic to change the CCX, AMD is a "small" company, they dont want to waste time re-engineering stuff to save a dollar or 2 in manufacturing costs. It goes completely against the idea of infinity fabric as well. They have a base block (the CCX) they will use it. All that time they waste on lowering performance ( removing L3) they could increase performance or lower power consumption by doing another physical/circuit tweak to the entire CCX.@itsmydamnation Yes, and it will have 'only' 8 GiB of L3$, which should be pretty small on 14LPP, certainly worth the space.
Hmm, this would break the architecture, but I suppose there could be a unified L2 tag 'cache' to save space.
All that time they waste on lowering performance ( removing L3) they could increase performance or lower power consumption by doing another physical/circuit tweak to the entire CCX.
If they planned on not including the L3 would be on the outside of the CCX. My point in comparing it to BD modules is that AMD designed the CCX to be a scalable module that they could use across their whole lineup. 4c (and maybe even 2c with 2c disabled), all the way up to 32c. The last thing they would do is rework the entire ccx design by removing the L3.I imagine if ends up being removed, having no L3 was a design option considered at the beginning. It wouldn't be a big deal to get it removed. But the die is going to be big enough as it is.
We could see two variants. The one with Vega GPU cores for mobile/embedded, and a desktop APU with Zen cpu cores plus, improved Polaris GPU, able to cross fire with the newly RX 500 series.
I can understand a Zen APU with Vega GPU cores towards mobile/embedded market. But not for desktop.
Desktop APU is considered entry level, that could become mainstream if cross fired with a dGPU. If the desktop APU has Vega GPU cores, that would mean it could only cross fired with Vega dGPU, which doesn't make sense, since Vega is considered enthusiast segment.
We could see two variants. The one with Vega GPU cores for mobile/embedded, and a desktop APU with Zen cpu cores plus, improved Polaris GPU, able to cross fire with the newly RX 500 series.