AMD Realizes Significant Reduction in Power Consumption by Implementing Cyclos Resona

[frostedflakes]

The link pm provided earlier actually has a breakdown of what consumes power on a chip, and the clock tree is a pretty huge chunk, 30% according to the figure. The paper seems to be talking more about ARM SoCs than desktop CPUs, though, so I don't know how relevant the figures would be to a high-frequency x86 CPU.

http://www.cyclos-semi.com/pdfs/time_to_change_the_clocks.pdf

 

[Abwx]

So assuming we take their numbers at face value - a 25% reduction in clock power consumption results in a 10% reduction in chip power consumption...Elementary math then says that clocks account for up to 40% of a cpu's power consumption.

True?

Less than 30% according to AMD , unless the CPU is iddling ,but perhaps that they did understimate the real world number when going from simulations to actual wafers...

 

[nenforcer]

I'm always a little hesitant when they integrate this new tech on an existing processor, when it doesn't appear to have been included from the start.

I'm hoping I don't have to skip Piledriver and wait for Steamroller in 2013.

 

[Idontcare]

I'm always a little hesitant when they integrate this new tech on an existing processor, when it doesn't appear to have been included from the start.

I'm hoping I don't have to skip Piledriver and wait for Steamroller in 2013.

From what I got out of the article, they integrated both clock types into piledriver. rclk and cclk. So if resonant clocking is borked, I suspect they could fall back to using the higher power-consuming clock method.

 

[sm625]

pm, refer to figure 11 of this paper: http://www.ece.ncsu.edu/asic/ece733/2011/docs/ResonantClock.pdf

I think that will explain better than words how they are able to reduce power consumption at 4GHz, and also help to explain why varying the frequency isnt really an issue. The power consumption is significantly higher at lower speeds such as 1GHz. That is the tradeoff. When this chip comes out we're going to want to look closely at the idle power.

 

[Zor Prime]

Hmm, if Idontcare is correct, perhaps AMD figured out a way to switch between the two methods of power consumption (for lack of a better phrase). One for full clock, the old standard for low-power.

Who knows. Would be nice to have a win-win in either situation, though. I sorta doubt they went that far, though.

 

[Idontcare]

Hmm, if Idontcare is correct, perhaps AMD figured out a way to switch between the two methods of power consumption (for lack of a better phrase). One for full clock, the old standard for low-power.

Who knows. Would be nice to have a win-win in either situation, though. I sorta doubt they went that far, though.

This is from the article:

To support testability and robust operation at the wide range of operating frequencies required of a commercial processor, the clock system operates in two modes: direct-drive (cclk) and resonant (rclk).

To operate in both modes, the clock driver needs to support frequency-dependent drive strength and pulse modulation, both of which are efficiently implemented using a split-buffer topology.

And ultimately the net benefits of the technology when reduced to practice:

The power savings from rclk enable either a frequency increase of about 100 MHz for the same power, or a power reduction of 5-10% for the same frequency.

Every little bit helps, but I have to admit I was kinda hoping for more than a mere 100MHz speed increase from the resultant power-savings. :\

 

[Abwx]

100mhz is not much , true...

The principle has a limitation , clearly showed by the power
saving curve in the ISSC paper.

The LC cell resonnance frequency is tuned thanks to variable
serial resistors built using fets;

To manage good efficiency these resistors value must be
low enough to ensure that damping is not excessively high ,
wich would render the resonnance weak and useless , but
even then , signal slew rates are clearly reduced as displayed
in the said paper.

What clearly appear is that the LC cell tuning is optimised for
higher frequencies where clocks bufferings power saving
make sense.

For overclockers , that might not be a good news as at
higher frequencies than the one targeted by AMD it is
likely that the LC cell become too slow , i.e , that the
auto tuning doesnt extend well when increasing frequencies
significantly higher than the stock one.

Probably that with maturing process and higher available
frequencies , the next Trinity revision will see a reduction
of the LC values to increase its average resonnance frequency
.

 

[podspi]

That could be a big boost from a yields POV.

Also, I assume (ok, hope) there are other modifications to improve perf/watt over BD.
AND then you also have the maturing 32nm process. Hopefully it all adds up to a solid increase over BD.

 

[krumme]

This is a wonder.
CPU engineers and process techs, work thousands of hours just to get 0.5% power reduction. I mean, how much hard super qualified work of the best in the indutri is not done for far, far, far less improvements?
Then, out of the blue sky, comes a nearly plug and play - simple and elegant - solution giving 5-10% total reduction from day one!, just working on the clock part.

 

[Olikan]

We were able to seamlessly integrate the Cyclos IP into our existing clock mesh design process so there was no risk to our development schedule

so... AMD was developing clock mesh?
i mean, bulldozer was beeind said to have great performance\watt
makes me wonder if bulldozer were supposed to have this, since the beggining

 

[MaxPayne63]

so... AMD was developing clock mesh?
i mean, bulldozer was beeind said to have great performance\watt
makes me wonder if bulldozer were supposed to have this, since the beggining

I think you just found the missing 800m transistors.

 

[gorydetails]

that explains alot

 

[GroundZero7]

So does this mean the performance estimate of Piledriver went up 20%?

+10-15% IPC improvment from Architecture and cache tweaks

+10% from Resonant clock mesh. Lower power = more overclocking headroom

+10% from Resonant clock mesh. eliminated clock skew = ~10% better overclocking.

+10-15% if you get Win8, from CMT

So +40% worst case , +50% best case.

I don't know if RCM is included in any official performance estimates yet since the news of it's inclusion in Piledriver and Trinity is only 2 days old.

If the release of this news coincides with the satisfactory testing of engineering samples Piledriver should be out by april. and with better yields than predicted

 

[Ancalagon44]

So does this mean the performance estimate of Piledriver went up 20%?

+10-15% IPC improvment from Architecture and cache tweaks

+10% from Resonant clock mesh. Lower power = more overclocking headroom

+10% from Resonant clock mesh. eliminated clock skew = ~10% better overclocking.

+10-15% if you get Win8, from CMT

So +40% worst case , +50% best case.

I don't know if RCM is included in any official performance estimates yet since the news of it's inclusion in Piledriver and Trinity is only 2 days old.

If the release of this news coincides with the satisfactory testing of engineering samples Piledriver should be out by april. and with better yields than predicted

I highly, highly doubt that. Highly, highly.

I'm expecting:
5-7% IPC gain
5-10% maximum clock speed gain
5-10 lower power consumption at the same clocks. In other words, because clock speeds are increasing, power consumption will remain the same.

AMD - fooled me once, shame on you. I wont be fooled again.

 

[GroundZero7]

You should read up on Piledriver. The changes from Bulldozer are signifigant.
http://support.amd.com/us/Processor_TechDocs/47414_15h_sw_opt_guide.pdf

 

[Ancalagon44]

So were the changes from Phenom II to BD, and look how that turned out.

JFAMD promised us higher IPC - look what happened! Last time I believe an AMD promise or marketing material. I'll believe official benchmarks published by Anandtech.

Source

Longer term, AMD has started talking up Bulldozer's first revision, Piledriver. Due next year, AMD projects that Piledriver will be about 10 percent faster than Bulldozer currently is. Piledriver will change some of the execution units to support additional floating point instructions, but is not expected to be a major overhaul of the processor's design.

 

[Idontcare]

so... AMD was developing clock mesh?
i mean, bulldozer was beeind said to have great performance\watt
makes me wonder if bulldozer were supposed to have this, since the beggining

The inductors have a tell-tall layout structure that can be seen in the die-map. See the picture on the last page of the presentation linked above, they clearly mark out where the inductors are in Piledriver. Those inductors are not present in bulldozer.

So does this mean the performance estimate of Piledriver went up 20%?

+10-15% IPC improvment from Architecture and cache tweaks

+10% from Resonant clock mesh. Lower power = more overclocking headroom

+10% from Resonant clock mesh. eliminated clock skew = ~10% better overclocking.

+10-15% if you get Win8, from CMT

So +40% worst case , +50% best case.

I don't know if RCM is included in any official performance estimates yet since the news of it's inclusion in Piledriver and Trinity is only 2 days old.

If the release of this news coincides with the satisfactory testing of engineering samples Piledriver should be out by april. and with better yields than predicted

The net effect on Piledriver was already reported by the AMD engineers as being a 100MHz increase if you keep the power usage the same, or a 5% decrease in power usage if you kept the clocks the same.

 

[Chiropteran]

The net effect on Piledriver was already reported by the AMD engineers as being a 100MHz increase if you keep the power usage the same, or a 5% decrease in power usage if you kept the clocks the same.

Compared to what, though?

For example, according to this-
http://www.legionhardware.com/articles_pages/amd_fx_8150fx_8120fx_6100_and_fx_4170,7.html

8150 uses 3% more power than 8120, but runs at 500mhz higher base clock. So why does Piledriver need 5% more power for a 100mhz increase? It doesn't really add up...

I'm assuming Piledriver will be a line of CPUs, not just one single CPU, so I don't understand how they can make such a statement- unless they are only talking about the top bin Piledriver CPU, but wedon't know what it's base speed was before the extra 100mhz or 5% power savings. If it's 100mhz more on top of a base speed of 5.5ghz, that is something different from 100mhz more than 3.6ghz.

 

[soccerballtux]

wow,,,reduced power 24 per cent,,,

only the clock cycle generation technology IE the crystals
this means nothing IMO

 

[taltamir]

AMD Realizes Significant Reduction in Power Consumption by Implementing Cyclos Resonant Clock Mesh Technology

AMD, not ARM, first to use startup's low-power clock IP

LONDON – Advanced Micro Devices Inc. has achieved the first commercial implementation of resonant clock mesh technology licensed from startup company Cyclos Semiconductor Inc.

Now, I might be imagining things... but last I checked piledriver was not yet launched.
I recall AMD claiming to be the first to do fusion or GPU hybrid power and in both cases by the time the actual product came to the market, their competitors have already released such items ahead of AMD.. just without the fanfare. (MS made the first fusion chips for xbox360, followed by intel SB, followed by AMD's. And with hybrid power, nvidia got hybrid power followed by optimus while AMD canceled the project)

All that being said, good for AMD for cutting down their power consumption.

 

[Haserath]

Just taking a stab at what I picked up from this.

From my understanding, the clock mesh is used to unevenly distribute clock signal through the circuit, since some parts of the entire IC need a stronger signal than others. This reduces overall clock power by needing less delivery power to the branches of the clock trees that don't need as much signal as other power hungry branches.

The resonating part of the resonance clock mesh just makes the signal stronger by using inductors to resonate it at a target frequency. Tuning the IC for that target frequency will make it more efficient at that frequency, but I'm not so sure about any other frequencies...

The capacitance of the clock mesh is the 'capacitor(s)' of this design(Each tree can store up a certain amount of electrical field to store energy). Each HCK tree is a step for the clock signal to repropagate through the circuit and distribute the signal accordingly.

That's just my take on this. Hopefully Piledriver will see some decent improvements other than just up to 24% reduced clock signal power and small IPC gains.

 

[joshhedge]

Now, I might be imagining things... but last I checked piledriver was not yet launched.
I recall AMD claiming to be the first to do fusion or GPU hybrid power and in both cases by the time the actual product came to the market, their competitors have already released such items ahead of AMD.. just without the fanfare. (MS made the first fusion chips for xbox360, followed by intel SB, followed by AMD's. And with hybrid power, nvidia got hybrid power followed by optimus while AMD canceled the project)

All that being said, good for AMD for cutting down their power consumption.

I am pretty sure that AMD/ATI makes the chips for the Xbox 360

 

[Joseph F]

NVM

 

[taltamir]

I am pretty sure that AMD/ATI makes the chips for the Xbox 360

Wrong, AMD designed the GPU originally but they sold the design to MS which has made changes. One of which was designing the worlds first APU based on that.
The xbox360 GPU underwent several optical shrinks before being integrated with the CPU into a single chip, along with a special "slow down module" which is designed to artificially slow down the CPU and GPU on the fusion chip to compensate for the speed improvements of the design over two seperate chips. It was slowed down to original xbox360 specs