Dresdenboy
Golden Member
That's the definition problem in more detail.And what specific instruction is being referred to?
We've got a lot to choose from, and the execution latencies varies widely across them in any given microarchitecture.
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So we'd need to define the instruction under consideration, or if it is to be more than one instruction then we must define the instruction mix (and weightings).
In short, its not simply an academic matter, that would actually be easier than the errand we are setting ourselves upon here.
We would be talking about defining our own Bapco sysmark or passmark with which "effective IPC" would be characterized, and it would be "workload class" dependent. IPC for office apps is different than IPC for mathlab apps because the instruction mix, and their weightings, are so different.
I assume internally AMD measures IPC while running SPEC benchmarks since they are mostly referring to them in regard of performance. This would include recompilation, which in turn means lower performance for unchanged "legacy" code. Since SPEC results have been published we even might verify their claim.
The ISSCC paper "40-Entry Unified Out-of-Order Scheduler and Integer" by M. Golden et. al. states:What the heck would "constant IPC" mean? To me it means "steady-state IPC", you process the exact same execution loop indefinitely and measure the average IPC that comes from doing so. But what instructions? And perhaps more importantly, to what end?
So in the context of a comparison with previous cores, they had one goal to maintain IPC. This should at least make clear that it's not about "steady-state IPC".Compared to previous AMD x86-64 cores [3-6], project goals reduce the number of FO4 inverter delays per cycle by more than 20%, while maintaining constant IPC, to achieve higher frequency and performance in the same power envelope, even with increased core counts.