AMD rumor

[Greenman]

This post says AMD can make your OS see 2 cores as one, and use them both.

Can this be done? Or is it fanboy BS?

http://www.xtremesystems.org/forums/showthread.php?t=103636


Edit: Forgot to mention, it would be awsome if true, but it sure seems like a pipe dream to me.

 

[DrMrLordX]

Stories about that have been going around since April or so, though this is the first time I've heard of the feature already being enabled in AM2 silicon. That seems like a stretch.

 

[dmens]

fanboy bs.

 

[OcHungry]

Originally posted by: Greenman
This post says AMD can make your OS see 2 cores as one, and use them both.

Can this be done? Or is it fanboy BS?

http://www.xtremesystems.org/forums/showthread.php?t=103636


Edit: Forgot to mention, it would be awsome if true, but it sure seems like a pipe dream to me.

Not true. If it was, AMD would have already mentioned it since desperately needs to compete w/ conroe. Such technology requires more than software patch and drivers or bios update. It's just AMD fanboysm.
It's time to concede to conroe or produce something that can compete. Or just hang it up for time being and sell dual cores for $75 or less to stay afloat.

 

[Vegitto]

It's not a rumour. As far as I know, Cooper's always been right. He was right with M2 --> AM2, he was right with DDR2-800, he was right with unlocked multi's for the FXes. He's always been right, and I don't think I'll start doubting him now.

I sure hope S939 has it too, though .

 

[zephyrprime]

I wish people wouldn't call it "anti-hyperthreading" or "reverse-hyperthreading". It's a very misleading term. Maybe "super-speculation" or "core speculation" would be better terms?

Anyway, the AM2 had a sizeably bigger die even though it didnt' really bring any significant new features. Could this be the reason why the die is bigger? Or maybe this is just a rumor.

 

[Griswold]

Originally posted by: zephyrprime

Anyway, the AM2 had a sizeably bigger die even though it didnt' really bring any significant new features. Could this be the reason why the die is bigger? Or maybe this is just a rumor.

Pacifica most likely. Maybe Pacifica can do more than just virtualization for an OS - like reverse-virtualization of two cores.

 

[DrMrLordX]

Yeah, one of the posters over at XS hinted that virtualization technology was related to "reverse hyperthreading" somehow (or super-speculation or whatever it is you'd like to call it).

Even still, I gotta see this in action before I'd believe it 100%.

 

[gobucks]

i have heard rumors about this, but not with current generation hardware. I think the earliest we could see anything like this would be K8L in late 2007 or whatever AMD's next gen hardware might be after that. I would imagine that at the very least, this technology would require a unified cache, something that AMD will not include at all until K8L, and even then it'll only be a unified L3 cache.

 

[BrownTown]

also, I really don't see much of a palce for this. Programs are all gonna be heading towards a parellel structure, so the biggest use would be for accelerating legacy code, but that code is designed for older CPUs, and would likely run fine even if it was only give 1 core. Also, the speedup would be very limited compared to explicitly parrellel code.

 

[RichUK]

Originally posted by: BrownTown
also, I really don't see much of a palce for this. Programs are all gonna be heading towards a parellel structure, so the biggest use would be for accelerating legacy code, but that code is designed for older CPUs, and would likely run fine even if it was only give 1 core. Also, the speedup would be very limited compared to explicitly parrellel code.

This could possibly benefit AMD quad cores (or further multi cores), if it were to act as two instances on the quad core for example.

I think this technology is more aimed at the Corporate domain anyway. For server environments, applications etc

 

[imported_Questar]

Originally posted by: dmens
fanboy bs.

QFT

 

[BrownTown]

Originally posted by: RichUK

Originally posted by: BrownTown
also, I really don't see much of a palce for this. Programs are all gonna be heading towards a parellel structure, so the biggest use would be for accelerating legacy code, but that code is designed for older CPUs, and would likely run fine even if it was only give 1 core. Also, the speedup would be very limited compared to explicitly parrellel code.

This could possibly benefit AMD quad cores (or further multi cores), if it were to act as two instances on the quad core for example.

I think this technology is more aimed at the Corporate domain anyway. For server environments, applications etc

But servers usually run very parellel code, this would be useless for them. Mostly just good for playing a single threaded game with a quad core. Also, like I said before, the speedup would be very small considered to the amount of additional resources being employed, it does make sense to try to use the additional cores to speedup others when they are not in use, but I think the headache it would casue would not be worth the effort.

 

[RichUK]

Originally posted by: BrownTown

Originally posted by: RichUK

Originally posted by: BrownTown
also, I really don't see much of a palce for this. Programs are all gonna be heading towards a parellel structure, so the biggest use would be for accelerating legacy code, but that code is designed for older CPUs, and would likely run fine even if it was only give 1 core. Also, the speedup would be very limited compared to explicitly parrellel code.

This could possibly benefit AMD quad cores (or further multi cores), if it were to act as two instances on the quad core for example.

I think this technology is more aimed at the Corporate domain anyway. For server environments, applications etc

But servers usually run very parellel code, this would be useless for them. Mostly just good for playing a single threaded game with a quad core. Also, like I said before, the speedup would be very small considered to the amount of additional resources being employed, it does make sense to try to use the additional cores to speedup others when they are not in use, but I think the headache it would casue would not be worth the effort.

Hmm I was more thinking towards my work (and not in general) with the many bespoke apps we have that are coded to only spawn two threads, thus my suggestion having this tech turning 4 cores into two faster cores would work (if this tech ever worked like this). Of course this has no relevance to the majority.

But in a more general standard and with the way things are headed I agree with your original points.

I suppose it boils down to how exactly this technology is going to be implemented by AMD, if it were to be configurable on a per app (within OS), or per server/workstation (within BIOS) basis. But yeah for current game code this would work well.

 

[MrFanel]

Biggest, load, off, BS, ever. Trust me on this, as someone who is in the know.


edit: crap - the heat is affecting me it's 100F here

 

[HurleyBird]

You mean in the know.

 

[F1shF4t]

As far as i see it prolly could be possible to do, i guess maybe make the program see one core with twise as many execution units instead of 2 cores. So both cpus will be used as one. For amd is prolly possible cause they have the crossbar and mem comtroler on the cpu. But it would require some tricky logic to make a single thread run on 2 cores.

Anyways what would be nice with this is if its able to switch always, ie on thread basis, cause that could improove even multithreaded program performance greatly. You cant always divide the prog to be multithreaded and each thread to have even load. So what this could allow is to make the more load thread use both cores while the second thread is waiting for input etc.


I donno if they can do it or if it is BS, but this tech has some really cool posibilities.

 

[MrFanel]

Originally posted by: Dark Cupcake
As far as i see it prolly could be possible to do, i guess maybe make the program see one core with twise as many execution units instead of 2 cores. So both cpus will be used as one. For amd is prolly possible cause they have the crossbar and mem comtroler on the cpu. But it would require some tricky logic to make a single thread run on 2 cores.

Anyways what would be nice with this is if its able to switch always, ie on thread basis, cause that could improove even multithreaded program performance greatly. You cant always divide the prog to be multithreaded and each thread to have even load. So what this could allow is to make the more load thread use both cores while the second thread is waiting for input etc.


I donno if they can do it or if it is BS, but this tech has some really cool posibilities.

This will not happen. Ever. Trust me; stop believing everything you hear from unreliable sources.

 

[Tangerines]

Intel is working on a technology called Mitosis, which is supposed to do the same thing.

 

[F1shF4t]

Originally posted by: MrFanel

Originally posted by: Dark Cupcake
As far as i see it prolly could be possible to do, i guess maybe make the program see one core with twise as many execution units instead of 2 cores. So both cpus will be used as one. For amd is prolly possible cause they have the crossbar and mem comtroler on the cpu. But it would require some tricky logic to make a single thread run on 2 cores.

Anyways what would be nice with this is if its able to switch always, ie on thread basis, cause that could improove even multithreaded program performance greatly. You cant always divide the prog to be multithreaded and each thread to have even load. So what this could allow is to make the more load thread use both cores while the second thread is waiting for input etc.


I donno if they can do it or if it is BS, but this tech has some really cool posibilities.

This will not happen. Ever. Trust me; stop believing everything you hear from unreliable sources.

LOL untill i see a hell of a lot of evidence supporting it i wont believe it.

Like i said i dont know if its even possible, well it IS possible but will the extra r&d u have to put into it produce good enough gains. And just another thing ARE u a reliable source that i should believe u that it will never be done?

This is all speculation, i'm just putting a few "what ifs" down.

 

[dmens]

Originally posted by: Dark Cupcake
LOL untill i see a hell of a lot of evidence supporting it i wont believe it.

Like i said i dont know if its even possible, well it IS possible but will the extra r&d u have to put into it produce good enough gains. And just another thing ARE u a reliable source that i should believe u that it will never be done?

This is all speculation, i'm just putting a few "what ifs" down.

HAHAHA, you want evidence? Go look at the K8L die plot, the fact that the floorplan is basically the exact same as a K8 means this crazy thing is NOT PRESENT. If it were, it'd look like a Cell on steroids.

Oh yeah, intel's mitosis *research paper* is just that, an academic paper. I have no doubt it can work, with unlimited power, die area, transistor budget and compiler support. But it'd make prescott's extended replay look efficient.

 

[Jeff7181]

I read about this a while back, and from what I remember the author of the article said it would be extremely difficult to make it happen... not only that, it would require too much die space to make it happen. Assuming that is still true, anyone who comes up with a way to do it without spending so much valuable die space would be a very rich company.

 

[Markbnj]

Originally posted by: BrownTown
also, I really don't see much of a palce for this. Programs are all gonna be heading towards a parellel structure, so the biggest use would be for accelerating legacy code, but that code is designed for older CPUs, and would likely run fine even if it was only give 1 core. Also, the speedup would be very limited compared to explicitly parrellel code.

Agreed. The trend is toward more threads running on more CPUs. I guess it might somehow benefit an embedded application that was doing one thing.

 

[F1shF4t]

Originally posted by: dmens

Originally posted by: Dark Cupcake
LOL untill i see a hell of a lot of evidence supporting it i wont believe it.

Like i said i dont know if its even possible, well it IS possible but will the extra r&d u have to put into it produce good enough gains. And just another thing ARE u a reliable source that i should believe u that it will never be done?

This is all speculation, i'm just putting a few "what ifs" down.

HAHAHA, you want evidence? Go look at the K8L die plot, the fact that the floorplan is basically the exact same as a K8 means this crazy thing is NOT PRESENT. If it were, it'd look like a Cell on steroids.

Oh yeah, intel's mitosis *research paper* is just that, an academic paper. I have no doubt it can work, with unlimited power, die area, transistor budget and compiler support. But it'd make prescott's extended replay look efficient.

Dude listen i said i will not believe the antihyperthreading or whateven it is until i see evidence of its existence. Where the hell did u get the idea that i was saying it is present in the k8L ???

If the only thing u can do is post BS about posts that u missread dont post at all. I'm trying to discuss why i think this could be a usefull tech to research into and i welcome anyone to discus why they either agree or dissagre.

Agreed. The trend is toward more threads running on more CPUs. I guess it might somehow benefit an embedded application that was doing one thing.

What about things which cant be effectively done in parrallel and take a lot of processing time, this is where i see this could be usefull.

 

[dmens]

Then why'd you say:

LOL untill i see a hell of a lot of evidence supporting it i wont believe it.

to a guy that posted:

This will not happen. Ever.

Indicating you want evidence the technology is not present before believing in such. Whatever, guess someone needs to learn how to read and spell.

And if you're interested in a technical discussion, you might want to start with codeflow instead of "tasks", because such a machine is doing instruction-level speculation.