AMD Ryzen 2000 (12nm Zen+) expectations

[Ancalagon44]

I have no other info than what is already available on the internet.
These numbers and features are not just pulled out of my a$$, but are precisely picked and polished having connection with reality and what's possible.

Okay, then just post a few links that you have read that contain some of this information please.

 

[gOJDO_n]

Those memory specs look high to me and I'm sorry but I don't see AMD matching CFL clock for clock on Zen+, let alone pulling ahead. Ryzen's memory latency is a lot higher than Intel's and when looking at max memory OC CFL is down in the mid to high 30ns range and Ryzens is double that. This is simply wishful thinking. AMD has always struggled with memory controllers, a 50% reduction in latency is a HUGE jump.

Zen+ will bring low single digit IPC improvements and a nice ~ 10-15% clockspeed bump but I don't expect anything more than that. If pricing stays the same Zen+ will be a phenomenal value but a lot of the claims in your post happening until 2019 with Zen2 and even then I'm not sure they will happen.

If you analyse this slide, like Anand did, you will find out that Ryzen was designed from the begining to run high DRAM clocks. Actually TR was planned to be released with a native 3200MHz support, but for other (chipset/mainboard/etc) reasons it was released with a slower native DDR4-2666, support, the same as EPYC. And server CPUs always have lower core and DRAM clocks in order to improve their stability and longevity.

As for the IPC, I was very precise in which cases I expect Zen+ CPUs to match or even surpass CFL, and it is in 4K gaming. And here I'm not only considering the average FPS, but also the minimum FPS, since in average FPS current Zen CPUs are already performing better @4K than the same clocked and with the same number of cores/threads CFL/SKL-X based CPUs:

https://www.techpowerup.com/reviews/Intel/Core_i7_8700K/18.html

The 1600X with 3.6/4/4.1GHz Base/All core boost/XFR on all cores performs in average like a 8700K with 3.7GHz/4.4GHz/4.7GHz. Ryzen 1600x not clearly matches 8700K performance with 10-15% clock disadvantage, it also kicks the crap out of i7-7820X which has 33% more cores and higher 3.6/4.3/4.5GHz base/all core boost/single-core clocks.

As for the memory controllers performance and efficiency, AMD were never behind and most of the time were ahead of Intel. AMD were the first to include IMC on their CPUs in 2003 with Athlon64/Opteron. 5 years latter, Intel followed that path. I don't want to derail my post talking about GPU industry where AMD were always steps ahead of the competition and was the primary player in most of the memory types/standards used up to date (gDDR3, gDDR4, gDDR5, HBM, HBM2, HBM3, etc). They have UMA/NUMA for years, and they have EPYC offering significantly better RAM capacity and bandwidth then Intel's best.

There are several issues which are resulting in Ryzen's lower gaming performance at 1080p or below and almost all are related to IF latency and bandwidth. The total per-direction bandwidth which CCX can get over the DataFabric of InfinityFabric is limited to IF clock * 256bit and that is the same as the RAM data rate * 128bit * 2. So when one CCX needs to read data from another CCX and from main memory at the same time, huge DF bottleneck occurs since the read/write is happening effectively at half the possible transfer rates and latencies are dramatically increased as well. Games are type of software which is mostly non-parallel and involves a lot of RAM accessing. That's why we see such huge gains in Ryzen's gaming performance when increasing the IF clock. Doubling the IF clock in Zen+ will double the bandwidth and will halve the access latencies. This will significantly fix Ryzen's performance in all games-like applications and will have impact in other types of applications on the CPUs with a MCM design where the added latency due to MCM design hurts performance further. (https://www.servethehome.com/amd-epyc-infinity-fabric-latency-ddr4-2400-v-2666-a-snapshot/)

50% reduction in absolute latency is achieved by doubling the clock while maintaining the same relative latencies.

Now, why I'm expecting IF2 with double the clocks of IF1? It's because IF links are actually PCIe links and to move from PCIe 3.0 to PCIe 4.0, IF needs 2x clock speed. Now, we have information about ADM 400 chipsets arriving this spring at the same time with the new Zen+ 12nm CPUs. Also we have a lot of rumors about AMD starting to use PCIe 4.0 in 2018. We also have information that AMD will improve gaming performance with the next iteration of Ryzen. Putting all the pieces to the puzzle are revealing IF2 with DF2 using PCIe 4.0 links. Moving form PCIe 4.0 ti PCIe 3.0 is very easy since it involves little modifications of the PCIe 3.0 standard.

 

[Topweasel]

Memory controller is already insanely good.
1. IF can/should be touched, we know that and main problem with ryzen is DF speed. We can see that IF speed help in gaming, so AMD must find solution to this problem (3:2 - IMC : F speed should help a lot). 2400MT/s - 1600MHz DF.

2. I don't know about you but Ryzen has good memory support already, but yes they can still improve it.


Next big thing worth upgrading will probably come with HBM on CPUs. If AMD can see GPU with 481mm^2 with 8GB of HBM for 400$ already, I can't see why CPU with ~200mm^2 16GB of HBM for 600-800$ would be impossible.

Since this thread is about next generation, I think AMD will improve memory latency (DF speed), improve support for higher clocks and thats it. We might be able to hit 60GB/s with Ryzen on dual channel. Like I said previously, APU is very interesting, since AMD has capable IMC.

IF won't be touched.

 

[ultima_trev]

As for the IPC, I was very precise in which cases I expect Zen+ CPUs to match or even surpass CFL, and it is in 4K gaming. And here I'm not only considering the average FPS, but also the minimum FPS, since in average FPS current Zen CPUs are already performing better @4K than the same clocked and with the same number of cores/threads CFL/SKL-X based CPUs:

https://www.techpowerup.com/reviews/Intel/Core_i7_8700K/18.html

The 1600X with 3.6/4/4.1GHz Base/All core boost/XFR on all cores performs in average like a 8700K with 3.7GHz/4.4GHz/4.7GHz. Ryzen 1600x not clearly matches 8700K performance with 10-15% clock disadvantage, it also kicks the crap out of i7-7820X which has 33% more cores and higher 3.6/4.3/4.5GHz base/all core boost/single-core clocks.

4K is going to be mostly GPU bottlenecked, not CPU. Lower res gaming better illustrates a CPU's strength. Also keep in mind far more people game at 1080P, if not less. 1440P and 4K are a niche at best.

 

[scannall]

4K is going to be mostly GPU bottlenecked, not CPU. Lower res gaming better illustrates a CPU's strength. Also keep in mind far more people game at 1080P, if not less. 1440P and 4K are a niche at best.

720p benchmarks? Really? It would be better to use benchmarks that are actually relevant to your use case. Like 4k gaming in my case. I'm not spending a mountain of money, just to use it on a potato monitor.

 

[gOJDO_n]

Next big thing worth upgrading will probably come with HBM on CPUs. If AMD can see GPU with 481mm^2 with 8GB of HBM for 400$ already, I can't see why CPU with ~200mm^2 16GB of HBM for 600-800$ would be impossible.

I don't see a reason why to use huge amount of HBM for CPU tasks, especially for today's modern CPUs which have excellent predictors and prefetchers. 1GB HBM2/HBM3 acting as Level 4 victim cache(just like the eDRAM is acting on Broadwell-E) will be more than enough to hold all the required data the CPU needs almost all of the time.

The use of HBM will require a separate IMC, which should be connected to IF and that means a lot macro-architectural redesigning, especially if DRAM IMC has to be kept at the same time. It will also involve package redesign which will cost significantly more due to the use of interposers. In addition to this, the HBM prices are very high and will not settle in near future. So using HBM on the CPU package has a point only on very high-end workstation and server CPUs. A single 1024bit HBM located between the multiple dies on the MCM designs. providing 256GB/s bandwidth at low latency will have dramatical impact on the performance of such design compared to the same design without HBM.

4K is going to be mostly GPU bottlenecked, not CPU. Lower res gaming better illustrates a CPU's strength. Also keep in mind far more people game at 1080P, if not less. 1440P and 4K are a niche at best.

Performance @720p is non-relevant for today. Anyway from the graph we can see that at lower resolution Intel SKL CPUs are spamming more FPS than AMD Zen CPUs. That doesn't necessary means you as a user will have better user experience with the Intel system.

If you check the rest of the summary gaming charts you will notice that as the resolution is increased, Ryzen CPUs tend to come closer to Intel's (same clocked and same number of cores/threads) and at 4K they even surpass them. According to that we may conclude that AMD CPUs have some kind of bottleneck preventing them to perform @ 720P similar to Intel CPU just like they do @1440p. And that bottleneck IMO is no other, but the crapped IF bandwidth/latency between the CCXs and between the CCXs and IMC. Zen+ with IF2 should fix this, and that's why I expect to see 10-20% better performance (the performance delta between Intel and AMD at low res) in games at lower resolutions.

 

[CatMerc]

@The Stilt a while ago claimed that his engineering board had an option to run at 2x IF speed if I'm remembering correctly. (Can you confirm please?)

If that's the case, there are a few thoughts I have.
Is this turned off for stability/errata reasons? If so, a Ryzen+ could have definitely fixed this, allowing four doubled IF clocks.

Or maybe it's turned off for power efficiency reasons? The performance gains from 2x IF speed might not be worth the extra energy required for the higher clocks, especially if voltages for that clock domain need to rise.

In such a situation, I do see the option of releasing two desktop SKU's. One being the high performace SKU's like we have now, and another being high efficiency SKU's ending with a T suffix (Their naming scheme already includes this). In such a setup, you can have high perf, or high efficiency, according to what you're looking for.

 

[Yotsugi]

@The Stilt a while ago claimed that his engineering board had an option to run at 2x IF speed if I'm remembering correctly. (Can you confirm please?)

If that's the case, there are a few thoughts I have.
Is this turned off for stability/errata reasons? If so, a Ryzen+ could have definitely fixed this, allowing four doubled IF clocks.

Or maybe it's turned off for power efficiency reasons? The performance gains from 2x IF speed might not be worth the extra energy required for the higher clocks, especially if voltages for that clock domain need to rise.

In such a situation, I do see the option of releasing two desktop SKU's. One being the high performace SKU's like we have now, and another being high efficiency SKU's ending with a T suffix (Their naming scheme already includes this). In such a setup, you can have high perf, or high efficiency, according to what you're looking for.

IF barely eats power.

 

[gOJDO_n]

@The Stilt a while ago claimed that his engineering board had an option to run at 2x IF speed if I'm remembering correctly. (Can you confirm please?)

If that's the case, there are a few thoughts I have.
Is this turned off for stability/errata reasons? If so, a Ryzen+ could have definitely fixed this, allowing four doubled IF clocks.

Or maybe it's turned off for power efficiency reasons? The performance gains from 2x IF speed might not be worth the extra energy required for the higher clocks, especially if voltages for that clock domain need to rise.

In such a situation, I do see the option of releasing two desktop SKU's. One being the high performace SKU's like we have now, and another being high efficiency SKU's ending with a T suffix (Their naming scheme already includes this). In such a setup, you can have high perf, or high efficiency, according to what you're looking for.

I don't know who The Stilt is, but I share your thoughts about the reasons why IF is clocked so low. The energy efficiency is one reason, and the stability/errata, especially on the MCM and multi socket-MCM designs, is the other.

Also there are other reasons why I expect IF2 to be the key performance upgrade. AMD talked first about 48 core and then about 64 cores EPYC CPUS. Having twice the IF bandwidth, which has scalable link width enables twice dies to be directly connected on the same package while maintaining the same bandwidth and halving the latency. If we take into account that 12nm FinFET LPP takes 15% less die area than 14nm FinFET LPP, I won't be surprised to see a 8 die MCM in the same socket package as EPYC/ThreadRipper.

 

[CatMerc]

IF barely eats power.

That's not a definite thing we can answer. It's handling pretty much everything that's not the cores themselves, moving around tens gigabytes of data constantly under load. Moving around data too much is the reason Fermi ended up being as power hungry as it was.

It wouldn't surprise me if IF is 10%-20% of the chip's TDP under load.

 

[The Stilt]

@The Stilt a while ago claimed that his engineering board had an option to run at 2x IF speed if I'm remembering correctly. (Can you confirm please?)

Nope.
The sandbox registers inside Zeppelin die have such option for debug purposes.

Most likely the reason behind the default 1:2 config is simply a compromise.
It is still not certain if the maximum MEMCLK limit (practically 3466MHz in the best case) on Zeppelin is due to the memory controller or the fabric itself.
If the fabric cannot reliabily run higher than ~1733MHz then obviously we're not going to see higher than 3466MHz MEMCLKs either.

If the fabric would be running at 1:1 ratio and the fabric indeed is currently the limiting factor, then running the fabric at 1:1 ratio would obviously be impossible since it would restrict the memory frequency to 1600-1733MHz as well.

Besides, the returns from higher than 1600MHz fabric clock (i.e. 3200MHz DRAM) are extremely diminishing. Above ~3000MHz the largest gains are achieved from tuning the DRAM timings.
At 2666MHz Ryzen has > 56% higher memory latency than CFL so there is a lot to improve on.

Obviously if the upcoming Ryzen parts are able to clock significantly higher than the current part can, then the performance scaling from the higher MEMCLK / fabric speeds should continue beyond the current ~3000MHz levels as well.

 

[wahdangun]

IF is NOT running at half IMC/RAM speed but its running @IMC/RAM speed.

so dunno where the misconception that IF run at 1:2 come from

 

[Insert_Nickname]

I'm not expecting much more then a refined design with all of the kinks worked out.

Perhaps an improved memory controller, with wider compatibility.

Other than the CPU peroformance improvements, the new AMD 400 series chipsets will bring greater and faster connectivity thanks to the doubled bandwidth to the CPU by the PCIe 4.0 x4 connection.

Very, very unlikely. The PCIe 4 standard has just been introduced. Besides PCIe 3.0 has more then enough bandwidth for everything coming of the FCH (SATA, USB and a few GP PCIe 2.0 lanes). Since Ryzen has a dedicated PCIe 3 x4 slot for NVMe drives that bandwidth doesn't have to be factored in. Unlike Intel...

Significant reduction in power consumption at iso clock, they might introduce a 45w TDB desktop range.

8C/16T 45W? Would make one killer HTPC/Home Server CPU. Yes, please...!

Well, the thing is, I am not getting full performance out of my 1700, I don't think it likes the memory I got for it as it won't run at higher than 2666 MHz even with latest bios. I suppose I could just get some Bdie memory, but I got the 1700 before the 1600 was out, as I wanted to do an AMD build and try Ryzen. So it was an earlier chip, might not have a very good memory controller, and I do not need 8 cores for the ryzen rig, just 6 faster ones for games.

I'm in the same boat as you. My 1700 will not run higher either. Since it's properbly one of the absolute first batches shipped (bought on launch day), perhaps certain early 1700's just have a slightly poorer then average memory controller?

I was also considering b-die memory, but I'd need 32GB, and prices are beyond astronomical for that here currently.

 

[CatMerc]

Nope.
The sandbox registers inside Zeppelin die have such option for debug purposes.

Most likely the reason behind the default 1:2 config is simply a compromise.
It is still not certain if the maximum MEMCLK limit (practically 3466MHz in the best case) on Zeppelin is due to the memory controller or the fabric itself.
If the fabric cannot reliabily run higher than ~1733MHz then obviously we're not going to see higher than 3466MHz MEMCLKs either.

If the fabric would be running at 1:1 ratio and the fabric indeed is currently the limiting factor, then running the fabric at 1:1 ratio would obviously be impossible since it would restrict the memory frequency to 1600-1733MHz as well.

Besides, the returns from higher than 1600MHz fabric clock (i.e. 3200MHz DRAM) are extremely diminishing. Above ~3000MHz the largest gains are achieved from tuning the DRAM timings.
At 2666MHz Ryzen has > 56% higher memory latency than CFL so there is a lot to improve on.

Obviously if the upcoming Ryzen parts are able to clock significantly higher than the current part can, then the performance scaling from the higher MEMCLK / fabric speeds should continue beyond the current ~3000MHz levels as well.

Thanks for clarifying!

 

[The Stilt]

IF is NOT running at half IMC/RAM speed but its running @IMC/RAM speed.

so dunno where the misconception that IF run at 1:2 come from

AMD's own terminology ties it to the effective MEMCLK (DDR), not the actual frequency.
Hence 1:2.

 

[CatMerc]

Also @The Stilt while for most applications the IF configuration is fine, latency sensitive ones like 7zip compression or gaming really struggle on Ryzen compared to Intel counterparts. You don't get much gains from higher mem clocks because you need to compromise memory timings, but if IF clockspeed was increased without reducing memory timings I do believe Ryzen would get nice gains in those areas.

 

[maddie]

That's not a definite thing we can answer. It's handling pretty much everything that's not the cores themselves, moving around tens gigabytes of data constantly under load. Moving around data too much is the reason Fermi ended up being as power hungry as it was.

It wouldn't surprise me if IF is 10%-20% of the chip's TDP under load.

Sure about that.

102.22GB/s @ 2pj/bit

I get 1.635W @ full speed die to die IF transfers.

 

[Glo.]

So, in essence, in perfect world, next generation Ryzen CPUs will have 400 MHz higher clock speeds, much higher Infinity Fabric clocks, and lower latency, at the same TDP/Power consumption, and with lower prices.

Too bad its only in perfect world .

 

[scannall]

So, in essence, in perfect world, next generation Ryzen CPUs will have 400 MHz higher clock speeds, much higher Infinity Fabric clocks, and lower latency, at the same TDP/Power consumption, and with lower prices.

Too bad its only in perfect world .

I expect Zen+ will clock a little higher. %10 or so is my *guess*. A little cleanup on the architecture, maybe another 5% IPC this time around. Price? About the same. Like Zen, it will be a solid product worth serious consideration if you are building something new. Zen 2 should be more exciting. Good thing it will also use the AM4 socket. ;-)

 

[CatMerc]

Sure about that.

102.22GB/s @ 2pj/bit

I get 1.635W @ full speed die to die IF transfers.

Yes I'm sure, because the die to die link isn't what I'm talking about. Moving around data is one the biggest power expenses in modern processors, many of NVIDIA's, Intel's, and AMD's, efficiency strides come from mitigating movement as much as possible. Modern caches aren't only there for performance.

 

[gOJDO_n]

Most likely the reason behind the default 1:2 config is simply a compromise.

Everything is a comrpomise.

It is still not certain if the maximum MEMCLK limit (practically 3466MHz in the best case) on Zeppelin is due to the memory controller or the fabric itself.
If the fabric cannot reliabily run higher than ~1733MHz then obviously we're not going to see higher than 3466MHz MEMCLKs either.

A 2:3 IFRAM divider will solve this. I don't think that the IF can't clock higher. IMHO the reason behind the conservative IF clocks is the power efficiency which was one of the key importances when Zen was designed. Doubling its speed will most probably quadruple its power consumption which is not a big problem for the desktop CPUs, but it is for the mobile and server derivates.

If the fabric would be running at 1:1 ratio and the fabric indeed is currently the limiting factor, then running the fabric at 1:1 ratio would obviously be impossible since it would restrict the memory frequency to 1600-1733MHz as well.

If the fabric was running at 1:1 IFRAM ratio, it was going to run @3200MHz when using DDR4-3200.

Besides, the returns from higher than 1600MHz fabric clock (i.e. 3200MHz DRAM) are extremely diminishing. Above ~3000MHz the largest gains are achieved from tuning the DRAM timings.
At 2666MHz Ryzen has > 56% higher memory latency than CFL so there is a lot to improve on.

The latency is not the only and the most important bottleneck caused by the low IF speed. The available bandwidth to the CCX is limited to the DRAM bandwidth, so when one CCX is accessing data of another CCX it is done with same bandwidth as the DRAM to CCX. Doubling of that bandwidth will complete all CCX-to-CCX transactions twice as fast, access to DRAM will be halved, and in a case when one CCX is accessing data from IMC only half of the DataFabric total bandwidth throughput is going to be used while the other half would be available for accessing L3 data of another CCX .

Very, very unlikely. The PCIe 4 standard has just been introduced. Besides PCIe 3.0 has more then enough bandwidth for everything coming of the FCH (SATA, USB and a few GP PCIe 2.0 lanes). Since Ryzen has a dedicated PCIe 3 x4 slot for NVMe drives that bandwidth doesn't have to be factored in. Unlike Intel...

Unfortunately it is very likely that we will see PCIe 4 mainboards next year if not this one:
https://www.tweaktown.com/news/59265/amds-next-gen-vega-20-uses-pcie-4-arrives-q3-2018/index.html
https://www.theregister.co.uk/2017/10/26/fore_pci_express_40_finally_lands/
https://www.servethehome.com/pci-sig-releases-pcie-4-0-version-1-0/

We had heard rumors that either Intel or AMD were thinking of supporting PCIe 4.0 in their 2017 server products.

 

[IEC]

I'm in the same boat as you. My 1700 will not run higher either. Since it's probably one of the absolute first batches shipped (bought on launch day), perhaps certain early 1700's just have a slightly poorer then average memory controller?

I was also considering b-die memory, but I'd need 32GB, and prices are beyond astronomical for that here currently.

I have a 1800X and a 1700 from launch as well as two 1700s, a 1600X, and a 1600 I sold. All would hit 3200 CL14 with Samsung B-die memory in a 2x8GB single rank configuration, even on the cheapest B350 motherboard.

2x16GB or 4x8GB is a different story and is more chip/motherboard dependent. Still possible, but less likely.

 

[maddie]

Yes I'm sure, because the die to die link isn't what I'm talking about. Moving around data is one the biggest power expenses in modern processors, many of NVIDIA's, Intel's, and AMD's, efficiency strides come from mitigating movement as much as possible. Modern caches aren't only there for performance.

Agree with you on data movement but:

What exactly is IF to you? ALL data movement on the processor?

Power cost for data movement inter-die is much more than intra-die, so a 1.635W is a by far worse case.
You specifically said IF using 20-30% TP, not the normal flow of L2 and L1 caches to processing pipelines. This happens for all processors and is additional to using the IF, or are you saying that absolutely all data flows through the IF?

 

[ozzy702]

Too much wishful thinking by OP. Zen+ will have 7-15% faster clock speeds, 0-5% IPC increase, absolutely no change to IF and slightly better memory support. That combo will be fabulous and an extremely competitive setup for AMD.

Zen2, sure, I can see some, maybe even all the speculation coming true but we're years out from that.

 

[Insert_Nickname]

I have a 1800X and a 1700 from launch as well as two 1700s, a 1600X, and a 1600 I sold. All would hit 3200 CL14 with Samsung B-die memory in a 2x8GB single rank configuration, even on the cheapest B350 motherboard.

2x16GB or 4x8GB is a different story and is more chip/motherboard dependent. Still possible, but less likely.

I should have clarified. I bought 2x8GB of Crucial/Micron memory at launch, standard dual rank DDR4-2666. My 1700+Crosshair VI will not run that at anything above 2400MHz. It simply will not, and believe me I've tried.

Reason for "needing" 32GB is simply, that I'll not waste money on what'd effectively be a side-grade with 16GB of b-die memory. That stuff is insanely expensive here. You can not directly compare US prices, but the premium is on the wrong side of 50% for b-die. And standard DDR4 is not exactly cheap here either, 32GB of the JEDEC standard variety will set you back at least the equivalent of $350.

On the positive side 2400MHz dual rank performs almost as well as single rank 3200MHz. Proof should be easy to find. The real advantage of b-die is the massively improved latency, which matter for gaming. But since gaming is a secondary concern on the system I can live with as is.