If you analyse this slide,
like Anand did, you will find out that Ryzen was designed from the begining to run high DRAM clocks. Actually TR was planned to be released with a native 3200MHz support, but for other (chipset/mainboard/etc) reasons it was released with a slower native DDR4-2666, support, the same as EPYC. And server CPUs always have lower core and DRAM clocks in order to improve their stability and longevity.
As for the IPC, I was very precise in which cases I expect Zen+ CPUs to match or even surpass CFL, and it is in 4K gaming. And here I'm not only considering the average FPS, but also the minimum FPS, since in average FPS current Zen CPUs are already performing better @4K than the same clocked and with the same number of cores/threads CFL/SKL-X based CPUs:
https://www.techpowerup.com/reviews/Intel/Core_i7_8700K/18.html
The 1600X with 3.6/4/4.1GHz Base/All core boost/XFR on all cores performs in average like a 8700K with 3.7GHz/4.4GHz/4.7GHz. Ryzen 1600x not clearly matches 8700K performance with 10-15% clock disadvantage, it also kicks the crap out of i7-7820X which has 33% more cores and higher 3.6/4.3/4.5GHz base/all core boost/single-core clocks.
As for the memory controllers performance and efficiency, AMD were never behind and most of the time were ahead of Intel. AMD were the first to include IMC on their CPUs in 2003 with Athlon64/Opteron. 5 years latter, Intel followed that path. I don't want to derail my post talking about GPU industry where AMD were always steps ahead of the competition and was the primary player in most of the memory types/standards used up to date (gDDR3, gDDR4, gDDR5, HBM, HBM2, HBM3, etc). They have UMA/NUMA for years, and they have EPYC offering significantly better RAM capacity and bandwidth then Intel's best.
There are several issues which are resulting in Ryzen's lower gaming performance at 1080p or below and almost all are related to IF latency and bandwidth. The total per-direction bandwidth which CCX can get over the DataFabric of InfinityFabric is limited to IF clock * 256bit and that is the same as the RAM data rate * 128bit * 2. So when one CCX needs to read data from another CCX and from main memory at the same time, huge DF bottleneck occurs since the read/write is happening effectively at half the possible transfer rates and latencies are dramatically increased as well. Games are type of software which is mostly non-parallel and involves a lot of RAM accessing. That's why we see such huge gains in Ryzen's gaming performance when increasing the IF clock. Doubling the IF clock in Zen+ will double the bandwidth and will halve the access latencies. This will significantly fix Ryzen's performance in all games-like applications and will have impact in other types of applications on the CPUs with a MCM design where the added latency due to MCM design hurts performance further. (
https://www.servethehome.com/amd-epyc-infinity-fabric-latency-ddr4-2400-v-2666-a-snapshot/)
50% reduction in absolute latency is achieved by doubling the clock while maintaining the same relative latencies.
Now, why I'm expecting IF2 with double the clocks of IF1? It's because IF links are actually PCIe links and to move from PCIe 3.0 to PCIe 4.0, IF needs 2x clock speed. Now, we have information about ADM 400 chipsets arriving this spring at the same time with the new Zen+ 12nm CPUs. Also we have a lot of rumors about AMD starting to use PCIe 4.0 in 2018. We also have information that AMD will improve gaming performance with the next iteration of Ryzen. Putting all the pieces to the puzzle are revealing IF2 with DF2 using PCIe 4.0 links. Moving form PCIe 4.0 ti PCIe 3.0 is very easy since it involves little modifications of the PCIe 3.0 standard.