Because IF is inherent of their whole development process from the very beginning. It's how inter CCX communication is handled, it's how intra CCX communication is handled, it's how cross die communication is handled, it how cross socket communication is handled. It how GCU communication is handled, it how GPU memory communication is handled. It's how GPU to GPU and it's how GPU to CPU communication is handled. AMD isn't going to change that on a whim. But just look at their GPU's an increase in width and faster ram. That's how AMD got the scalable to ~500GB/s. It's link to memory is part of it's standard now and expecting AMD to change it cause a bunch guys on the Internet are absolutely sure that it is why games don't run as well as they think it should is a pipe dream. If anything AMD will make the pathway wider on future Zen archs. Won't be Zen+ and probably not Zen 2. But if AMD could or was willing to change the ratio or just plain set a speed Zen and Vega wouldn't have the exact same policy. AMD made a judgement call when developing IF that finding a bandwidth that was acceptable for CPU's and hit their goals on Vega and went with that. Otherwise you increase the complexity decrease yields on vega just to increase the performance on Zen and again that assumes what we see is caused by IF and not for example the L3 system they are using. You know the same one Intel adopted on SL-X that sees a similar drop in performance compared to expectations.
Sure it is. But people act like it's the end of the world if it's not absolutely the end all be all in all avenues. AMD had goals and performance markers they needed to hit. This includes things like power usage, Yields, the ability for IF to work on every layer. Like all CPU designs that means trade-offs and compromises. Memory and core to core latency where obviously part of that and their impact on the big picture probably isn't that large.
This isn't about AMD saying gaming is unimportant. They aren't going to ignore us (though I think it would be better if they did). But they aren't going to prioritize that if it threatens their long term goals.
I expect AMD will work hard on tweaking what little they are going to touch on Zen+. I expect some decent arch changes going into Zen 2. But I doubt any of those is going to deal with IF outside increase width in the die. Not unless they are ready to change out all the impacted systems at the same time. That means new die for Ryzen, new Die for APU's, new arch for video.
That is silly though. We know Ryzen doesn't have the memory Latency an i7 has, so that means that it's Ryzen's issue? It also doesn't have the L3 configuration. It also doesn't have a ring bus. Hell it's CPUID isn't GenuineIntel, maybe that is the reason? I am all for figuring out what is causing the performance rift and having AMD fix that as long as it doesn't hurt them in another way. This "I know what the answer is even though I have never built a CPU, or developed a game, just saw a difference (and I'll admit there is a large amount of people that agree) and used that as fact".It is bothersome because it could be blinding people from the real issue.
I haven't checked out as many Coffee lake reviews as I probably should. I do know KabyLake within about 2% or so saw the same increases in performance as Ryzen when using faster memory. I don't know but have no reason to believe otherwise the CoffeeLake as KBL with 2 extra cores would behave any differently. As for your link I am not going to watch the whole thing (this reviewer isn't my style) but I skimmed through the video and didn't find a single test with the same CPU using 2 speeds of memory, can you give me the time stamp of when he did?
I was quite busy for the weekend, so excuse my late reply to your post.
First, lets clarify what DataFabric is and how it works. It is a is a multiple coherent point-to-multi point HyperTransport links connecting all the I/O, DRAM and CCX L3 caches in the system. According to the current, HTX 3.1, standard, the rated speed of the HT 3.1 links is 6400MT/s or 3200MHz. So such DF speeds are not a question of possibility, but a a question of decision. Since the same HT links are used as PCI-e links and since PCI-e 4.0 requires 2x the clock of PCI-e 3.0, the HT links of DF has to be clocked double, which translates to doubling the IF throughput and reducing (by half?) the access latency.
The logic of IF funcitioning will remain the same, the way of how CCXs, I/O and DRAM are connected will remain the same, everything will remain the same! Just the DF clock will be doubled, its operating votatge increased. In addition minor changes will be made for the PCI-e 4 support.
As for the memory latency. One of the major differences between KBL/CFL and Ryzen michroarchitectures is that SKL/KBL/CFL have single L3 cache where all the cores are communicating directly through the L3 at it's full speed and low latencies, while on Ryzen it is separated in multiple CCX's which are connected via IF(which adds latency) and very slow HT link(at 10% of the potential inter-L3 core bandwidth). That low IF bandwidth the CCX are sharing for all the L3 to L3, I/O and DRAM communication, where the DRAM alone can fully saturate the HT Link to the CCX.
So the point is that Ryzen takes two advantages from the faster DRAM(and DF) clock:
1) It gives more RAM bandwidth to cores
2) It gives more L3 to L3 bandwidth and reduces reduces the absolute access latency
That's why Ryzen enjoys more performance improvement of faster RAM than SKL/KBL/CFL.
Back in the days, I did some performance testing and comparison on Skylake 6700K and different DDR4 modules (from 2133 to 3733):
https://www.it.mk/z170-ddr4-ram/
I came to the conclusion that there is no point of buying faster DDR4 than 3000MHz even with OC-ed CPU because it gives no performance improvements over the 3000MHz CL16 DDR4.
I can't say the same for Ryzen TR 1950X. It gains performance almost linearly from 2400 to above 3200MHz DDR4.