AMD Ryzen 2000 (12nm Zen+) expectations

[PeterScott]

Eh, 10% (From current 1800x base) more is closer to 4.1 Ghz. 4.4 on a golden chip? Possible, though probably not very likely.

I think people are more concerned with OC speed. Most consider the current batch to be 4GHz chips...

 

[gOJDO_n]

I don't expect that there will be any changes to IPC in Pinnacle Ridge, unless the current silicon revision still contains errata which deteriorates the IPC. Based on Raven's performance it is extremely unlikely that it does.

Errata is addressing bugs and in very rare cases the workarounds for those bugs have real-life impact on performance (like the TLB bug in the first Phenom Rev B2). If AMD decided to improve the Data Fabric in Zen+ (by doubling its bandwidth and reducing its latency) I expect modest IPC gains(5-10% in average) only in non-parallel apps which are sensitive to RAM bandwidth and latency like games.

The Fmax (both factory and end-user side) has to improve by >= 15% compared to current die revision, however I expect ~5% improvement at best. Unless of course AMD found some ways to tune the design itself, so that they can juice even more out of the limited process.
GlobalFoundries says "10% higher performance (at ISO power) compared to 14nm LPP", however it is impossible say if the actual Fmax is higher than on 14nm LPP based on that.

They said 10% higher performance compared to 16nm FinFET, but never stated to which 16nm Fin FET and what performance (nmos or pmos?).
Anyway, just like you said, 10% higher average transistor performance doesn't translates into 10% higher CPU frequency. The CPU frequency depends of slowest stage or the stage with the highest cumulative propergated delay in the CPU pipeline. Without circuit redesign by using 10% faster transistors I (just like you) expect no more than 5% higher CPU clocks. I believe AMD will make some circuit design improvements and fixes, but I don't expect those changes to have tangible impact on the CPU clocks .

 

[The Stilt]

They said 10% higher performance compared to 16nm FinFET, but never stated to which 16nm Fin FET and what performance (nmos or pmos?).
Anyway, just like you said, 10% higher average transistor performance doesn't translates into 10% higher CPU frequency. The CPU frequency depends of slowest stage or the stage with the highest cumulative propergated delay in the CPU pipeline. Without circuit redesign by using 10% faster transistors I (just like you) expect no more than 5% higher CPU clocks. I believe AMD will make some circuit design improvements and fixes, but I don't expect those changes to have tangible impact on the CPU clocks .

Funny how all of the slides indeed compare 12nm LP to "industry 16nm FinFet solutions", however in their press release GlobalFoundries mentions 14nm as well: "The new 12LP technology provides as much as a 15 percent improvement in circuit density and more than a 10 percent improvement in performance over 16/14nm FinFET solutions on the market today".

https://globenewswire.com/news-rele...nology-for-High-Performance-Applications.html

 

[exquisitechar]

Funny how all of the slides indeed compare 12nm LP to "industry 16nm FinFet solutions", however in their press release GlobalFoundries mentions 14nm as well: "The new 12LP technology provides as much as a 15 percent improvement in circuit density and more than a 10 percent improvement in performance over 16/14nm FinFET solutions on the market today".

https://globenewswire.com/news-rele...nology-for-High-Performance-Applications.html

What do you think about this?

14LPP had 3 options -

https://pc.watch.impress.co.jp/docs/column/kaigai/733713.html
https://pc.watch.impress.co.jp/img/pcw/docs/733/713/html/9.jpg.html

1. High Density (CPP=78nm,9T)
2. High Performance (CPP=84nm, 9T) and
3. Ultra High Performance (CPP=84nm, 10.5T)

AMD chose to go with High density for the first gen Zen die which was shared by client and server.

https://www.pcper.com/news/Processors/AMD-Details-Zen-ISCCC

A CPP of 78nm confirms Zen used High density libraries.

Pinnacle Ridge is a client only die built at 12LP. 12LP is an improved 14LPP node with transistor level enhancements. AMD has the choice to go for UHP libraries which has higher track height and larger CPP . We have to wait and see what AMD has done. But i think AMD might have gone for the max performance as they want to reduce the ST perf lead of Intel KBL and CFL.

I think raghu78 may be on to something. With Pinnacle Ridge being client only, AMD is likely to have gone with maximum performance in mind this time around. Improving Ryzen's ST performance to allow it to hold the fort until the massively improved Zen 2 arrives in 2019 seems like it should be a goal for AMD in the short term. I'm not expecting massively higher clocks, but a substantial gain seems like a possibility.

 

[ahimsa42]

so this is more a question about zen 3-specifically the APU (previously named Greyhawk) with Navi coming out in 2019-2020. if it does have HBM as was rumored, is there a possibility that the desktop version's integrated GPU could reach GTX 1060 level's? if so, i can imagine it in a mini PC which would suffice for most anyone but hard core FPS gamers.

 

[raghu78]

Desktop Ryzen?
You mean AMD would have ditched Zeppelin and designed a new die altogether?

Definitely possible. Pinnacle Ridge is a client only die. AMD can optimize the circuit layout removing unnecessary I/O as PR only needs to support connecting to one another die for TR instead of 3 more for EPYC. btw Stilt you have to remember Zeppelin used 14 LPP High density libraries (CPP=78nm MMP=64nm 9T) as AMD prioritized density and efficiency at lower clocks for EPYC over higher max clocks for Ryzen. There were other options such as 14 LPP High performance (CPP=84nm MMP=64nm 9T) and 14 LPP Ultra high Performance (CPP=84nm MMP=64nm 10.5T). With 12LP AMD and GF have designed a High performance process for Ryzen. So don't jump to conclusions on Fmax based on 14LPP high density Zeppelin die.

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[The Stilt]

Definitely possible. Pinnacle Ridge is a client only die. AMD can optimize the circuit layout removing unnecessary I/O as PR only needs to support connecting to one another die for TR instead of 3 more for EPYC. btw Stilt you have to remember Zeppelin used 14 LPP High density libraries (CPP=78nm MMP=64nm 9T) as AMD prioritized density and efficiency at lower clocks for EPYC over higher max clocks for Ryzen. There were other options such as 14 LPP High performance (CPP=84nm MMP=64nm 9T) and 14 LPP Ultra high Performance (CPP=84nm MMP=64nm 10.5T). With 12LP AMD and GF have designed a High performance process for Ryzen. So don't jump to conclusions on Fmax based on 14LPP high density Zeppelin die.

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Wouldn't moving from HD to HP require significant changes to the design also?
Might not be worth significant efforts, especially if the resulting design would be only used in products of a single segment and more importantly if the resulting design is just a raft / gap filler (i.e. a refresh) prior the next gen. Zen design.

I'm not drawing any conclusions about the Fmax based on the current Zeppelin die, but based on all relevant designs made on 14nm LPP. They all illustrate similar characteristics.

 

[Mulrian]

I think people are more concerned with OC speed. Most consider the current batch to be 4GHz chips...

At most. If you look at most people on Reddit for example there really aren't that many people hitting 4ghz - and even then not without pushing a lot of voltage. The most common overclocks are the 3.8-3.9 mark.

 

[raghu78]

Wouldn't moving from HD to HP require significant changes to the design also?
Might not be worth significant efforts, especially if the resulting design would be only used in products of a single segment and more importantly if the resulting design is just a raft / gap filler (i.e. a refresh) prior the next gen. Zen design.

I'm not drawing any conclusions about the Fmax based on the current Zeppelin die, but based on all relevant designs made on 14nm LPP. They all illustrate similar characteristics.

Of course there will be redesign involved but AMD have the resources to invest especially given that PR, Raven Ridge refresh called Matisse in 2019 and the upcoming 2C/4T 3CU Banded Kestrel SoC's refresh in 2019 are all likely to use 12LP. Moreover Mark Papermaster stated that Zen will be tock tock tock in cadence.
I think PR will bring a significant increase in max turbo and max clocks along with minor IPC gain.
https://www.extremetech.com/computi...ils-overclocking-plans-emphasizes-hard-launch

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[gOJDO_n]

AMD can optimize the circuit layout removing unnecessary I/O as PR only needs to support connecting to one another die for TR instead of 3 more for EPYC.

TR is using two links for connecting the dies and has twice die-to-die bandwidth compared to EPYC.

 

[CatMerc]

Wouldn't moving from HD to HP require significant changes to the design also?
Might not be worth significant efforts, especially if the resulting design would be only used in products of a single segment and more importantly if the resulting design is just a raft / gap filler (i.e. a refresh) prior the next gen. Zen design.

I'm not drawing any conclusions about the Fmax based on the current Zeppelin die, but based on all relevant designs made on 14nm LPP. They all illustrate similar characteristics.

I do imagine it would be worth it to keep the Ryzen momentum gained in 2017, keep it in consumers minds. But I'm obviously biased.

Either way, Pinnacle has options for significant clock uplifts without too much work, the question is if AMD took the opportunity. They might not have the resources even for that.

As a note, IIRC Carrizo went from barely 4GHz OC to 5GHz OC in Bristol. I'm not sure if how was ever disclosed though.

 

[moinmoin]

Pinnacle Ridge on 12LP going for high performance instead high density would be the perfect excuse for both Epyc and Ryzen Mobile/Raven Ridge to keep using the efficiency optimized high density 14LPP node. If AMD indeed does that it's likely that the fmax improvement afforded by a supposed high performance 12LP is more favorable than the efficiency improvement by a supposed high density 12LP.

 

[raghu78]

Pinnacle Ridge on 12LP going for high performance instead high density would be the perfect excuse for both Epyc and Ryzen Mobile/Raven Ridge to keep using the efficiency optimized high density 14LPP node. If AMD indeed does that it's likely that the fmax improvement afforded by a supposed high performance 12LP is more favorable than the efficiency improvement by a supposed high density 12LP.

12LP is a process like 14LPP with multiple track height options from 7.5T to 9T and probably even higher as GF refused to disclose maximum track height library offered at 12LP. GF also refused to disclose maximum Contacted Poly Pitch . I requested both these pieces of information through Daniel Nenni of semiwiki and GF refused to give out the information. So GF could be supporting multiple CPP based on high density and high performance. 14LPP already supported 78nm 9T (high density) and 84nm CPP 9T (High performance) and 84nm CPP 10.5T (Ultra high performance). So every process supports a range of libraries and the choice of library determines the tradeoffs.

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