Does not look good if you ask me.https://www.anandtech.com/show/680/6
According to Anand, Intel is at 10 GHz long way back so AMD better get those clocks up.
Reveal is on Monday
https://videocardz.com/75489/amd-ryzen-7-2700x-pictured-full-review-on-monday
XD
Does not look good if you ask me.
It’s worth noting that all SDF components run at the DRAM’s MEMCLK frequency. For example, a system using DDR4-2133 would have the entire SDF plane operating at 1066 MHz. This is a fundamental design choice made by AMD in order to eliminate clock-domain-crossing latency.
Could also mean the L3 within the CCX isn't tied to core clock. it used to run at the fastest cores clock.According to CPC
They seem to suggest that a modified uncore for improved memory access, would this mean IF and MEMCLK no longer tied to each other?
From WikiChip for Ryzen Gen 1, I believe.
I spotted an Internet Strongman in the comments of that Reveal article.https://www.anandtech.com/show/680/6
According to Anand, Intel is at 10 GHz long way back so AMD better get those clocks up.
Reveal is on Monday
https://videocardz.com/75489/amd-ryzen-7-2700x-pictured-full-review-on-monday
XD
You do him a great disservice! He is an internet super hero to give him his proper and full title .I spotted an Internet Strongman in the comments of that Reveal article.
That's my guess.Could also mean the L3 within the CCX isn't tied to core clock. it used to run at the fastest cores clock.
That's my guess.
I spotted an Internet Strongman in the comments of that Reveal article.
videocardz said:https://videocardz.com/newz/hwinfo-gets-support-for-amd-starship-and-mattise-cpus
https://videocardz.com/72934/rumor-amd-matisse-picasso-vega-20-and-ryzen-5-pro-mobile
https://videocardz.com/75217/amd-ry...astle-peak-matisse-picasso-vermeer-and-renoir
https://videocardz.com/69428/amd-snowy-owl-naples-starship-grey-hawk-river-hawk-great-horned-owl
https://videocardz.com/75231/amd-ryzen-threadripper-3000-to-take-a-leadership-in-hedt-market
From the AMD Teleconference Lisa Su was asked about the confidence AMD has with TSMC as a supplier of the 7nm Epyc products. Lisa responded that AMD would use both TSMC and Global Foundries for it 7nm products and TSMC would go first. Lisa also said AMD has confidence in TSMC.
https://twitter.com/2901bitslice/status/989275561364082688
From the AMD Teleconference Lisa Su is asked about Servers. Will 7nm Epyc ship this year. Is the Mid Single Digit including 7nm. Answers No and No. 7nm Epyc will Sample this year and ship in volume in 2019. They can get to Mid Single digit share with the current generation Epyc.
https://twitter.com/2901bitslice/status/989268837055975425
Vega 20 is being fabbed at TSMC. Have to think Navi is being fabbed there too.
BTW I think GloFo made some of the same mistakes that Intel did. Which is why the only product you will see from AMD at 7 nm GloFo in 2019 is Matisse, which can be chopped quite nicely. And why they are mentioning 48 cores even though it likely has a 16 core die.
Picasso (the APU) is being fabbed at GloFo 12.
A processing core of a plurality of processing cores is configured to execute a speculative region of code a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.
[0001] Hardware Transactional Memory (HTM) is a mechanism in computer architecture for supporting parallel programming. With HTM, programmers may simply declare a group of instructions as being part of a single speculative region and the HTM hardware may then guarantee that the instructions in the region are executed as a single atomic and isolated transaction. Atomicity means that all the instructions of the transaction are executed as a single atomic block with respect to all other concurrent threads of execution on one or more other processing cores in the system. Isolation means that no intermediate result of the transaction is exposed to the rest of the system until the transaction completes. HTM systems may allow transactions to run in parallel as long as they do not conflict. Two transactions may conflict when they both access the same memory area and either of the two transactions writes to that memory area.
[0002] To implement HTM, significant complexity must be added to processors and/or to memory subsystems. To deal with this complexity, processor architects have traditionally limited the feature set of a processor that implements HTM. For example, traditional HTM processors cannot utilize out-of-order execution optimizations while executing a speculative region of code. Out-of-order optimizations allow a processor to exploit instruction-level parallelism by executing instructions out of program order, temporarily storing the results of those instructions, and then writing the results to the memory hierarchy when all preceding instructions have done so. Since HTM processors do not use out-of-order execution to execute instruction sequences that are inside of speculative regions, traditional HTM processors may not execute instruction sequences in speculative regions as quickly as would otherwise be possible.
Zen 3 's TSX ?
ikr smh all these bois being hyped up about a ryzen thats 5 ryzens away from you, that's like a ryzen 1600 away from you, why are people so excited
Doodsicle - u didn't use enough werds or abbs; he'll never understand ur reply.I am not sure what you meant.
But I believe lots of people in the forum are interested in processor technology be it conceptual or in silicon. So to me it seems normal to talk about processor design in a tech forum.
Nice find, that patent. AMD's own ASF (Advanced Synchronization Facility) from 2009 predates it, though the instructions were never implemented (but the tech probably was seeing how AMD wasn't affected by Spectre's privilege escalations).Similar in many aspects to Intel's TSX.
AMD on 7nm
But no 7nm EPYC this year
Ryzen 5 2600E and Ryzen 7 2700E 45W 6C/8C on the way, at respective 3.1 and 2.8GHz frequencies :
https://www.computerbase.de/2018-05/ryzen-5-2500x-ryzen-3-2300x-amd-cpu/
No...... i dont know how you got that.So the roadmap change again, and AMD will sample epyc this year on TSMC
You just can't move SOC's from one foundry to the other, especially very high performance ones where you do custom work with the foundry partner which is a given for both AMD's two main SOC products.
Hitting the same sizes for basic building blocks (sram etc) would obviously help with a port, if you had to redo the layouts of everything then its like starting your physicals from scratch twice. But there are still other things like custom work for power distribution etc that will be very process and foundry specific.I know, but it sounds like GloFo is accommodating AMD's desire to work at TSMC and is working to make AMD's TSMC designs easier to port back to GloFo.
Maybe what happened is that they did a 12 core design at GloFo, and then later did a 16 core version at TSMC. Since TSMC is obviously farther ahead they are going with the TSMC design and convinced GloFo to make changes so they can reuse the design there. Sounds crazy but you never know.
Exactly. There is no way AMD is doing the same design at TSMC and GF. AMD simply does not have the resources to do that. AMD has confirmed Vega 7nm at TSMC. There was a digitimes articles saying that Navi is at TSMC.No...... i dont know how you got that.
What AMD is doing is shifting some products back to TMSC, it is very unlikely that AMD will make the same SOC at two different foundries(big waist of money). If you think about it logically its more likely that Zepplin follow on will be made at GF and maybe Raven ridge follow on + some/all GPU's + console SOC's are made at TMSC.
You just can't move SOC's from one foundry to the other, especially very high performance ones where you do custom work with the foundry partner which is a given for both AMD's two main SOC products.
This way they limit the rework but still get a benefit from the said rework (shipping PC SOC's on TMSC). Given what we know about intel 10nm and their server and high end desktop products, regardless of 12/48 or 16/64 core configs AMD isn't going to have much of a problem filling GF's 1 7nm facility with just that one SOC.