AMD Ryzen Gen 2 Set For Q2 2018

[CatMerc]

Exactly. There is no way AMD is doing the same design at TSMC and GF. AMD simply does not have the resources to do that. AMD has confirmed Vega 7nm at TSMC. There was a digitimes articles saying that Navi is at TSMC.

http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=threads/amd-navi-at-tsmc-7nm.2524108/

My guess is 7nm Rome is at TSMC. 7nm Ryzen CPUs and APUs are likely to be built at GF. This way AMD splits their designs across TSMC and GF to maximize their wafer allocation. TSMC is already in HVM at 7nm so the products built there will launch first. My guess is Vega 7nm in Q1 2019, Navi in Q2 2019, Rome in mid 2019.

https://www.semiwiki.com/forum/content/7496-imec-technology-forum-gary-patton-globalfoundries.html
https://www.eetimes.com/document.asp?doc_id=1333326&page_number=2

GF is in risk production on 7nm by mid 2018. Gary Patton,CTO of GF has confirmed they will be taping out their first 7nm chip - an AMD CPU in H2 2018. My guess is Q3 2018 tapeout. So Ryzen CPUs are likely to launch in mid to late Q3 2019 and Ryzen APUs in late Q1 2020.

Lisa said they'll come to market with whichever fab is ready first. For that to be the case they'd need to already have designs taped out at both fabs.
You grossly overestimate the cost of taping out new dies and underestimate AMD's ability to get it done.

Yes optimization is a major concern, but the cost to do it on both is worth it if it means you minimize TTM risks on arguably your most important product in years. 7nm EPYC will be as its name implies if Intel doesn't get their 10nm sorted, and so far things aren't looking positive on that end. And even if they do get it sorted, 7nm EPYC still has a very good chance to be a performance crown design.

 

[Glo.]

Wisest conclusion about 7 nm designs:

AMD will use higher TSMC for higher performance Chips(Ryzen 5/7 and X models), and GloFo for the ones are supposed to be lower performance(Non-X, Ryzen 3/5).

 

[CatMerc]

Wisest conclusion about 7 nm designs:

AMD will use higher TSMC for higher performance Chips(Ryzen 5/7 and X models), and GloFo for the ones are supposed to be lower performance(Non-X, Ryzen 3/5).

I wouldn't call it wise. TSMC isn't hitting their performance targets according to ARM, and GF's 7nm is also made for IBM with IBM engineers. I expect GF's process to outperform TSMC's.

 

[raghu78]

Lisa said they'll come to market with whichever fab is ready first. For that to be the case they'd need to already have designs taped out at both fabs.
You grossly overestimate the cost of taping out new dies and underestimate AMD's ability to get it done.

Yes optimization is a major concern, but the cost to do it on both is worth it if it means you minimize TTM risks on arguably your most important product in years. 7nm EPYC will be as its name implies if Intel doesn't get their 10nm sorted, and so far things aren't looking positive on that end. And even if they do get it sorted, 7nm EPYC still has a very good chance to be a performance crown design.

Firstly TSMC N7 is in HVM and much further ahead than GF 7LP which is just starting risk production. Secondly TSMC N7 HPC 7.5T is rumoured to have CPP =64nm . I heard in semiwiki forums.

Gary Patton, CTO of GF has confirmed they will tapeout their first 7nm chip - an AMD CPU later this year.

https://www.semiwiki.com/forum/content/7496-imec-technology-forum-gary-patton-globalfoundries.html

https://www.eetimes.com/document.asp?doc_id=1333326&page_number=2

So that should clarify that Zen 2 for servers which launches first is at TSMC N7.

GF 7HPC is a 9T library. So the designs will not be easily portable across TSMC and GF. Moreover I also have my doubts if TSMC N7 6T is sufficient for Rome given the comment from ARM fellow on very low wire speed gain over 16FF+. I think Rome will use N7 HPC 7.5T and aim for max turbo clocks of 3.6 Ghz.

 

[CatMerc]

Firstly TSMC N7 is in HVM and much further ahead than GF 7LP which is just starting risk production. Secondly TSMC N7 HPC 7.5T is rumoured to have CPP =64nm . I heard in semiwiki forums.

Gary Patton, CTO of GF has confirmed they will tapeout their first 7nm chip - an AMD CPU later this year.

https://www.semiwiki.com/forum/content/7496-imec-technology-forum-gary-patton-globalfoundries.html

https://www.eetimes.com/document.asp?doc_id=1333326&page_number=2

So that should clarify that Zen 2 for servers which launches first is at TSMC N7.

GF 7HPC is a 9T library. So the designs will not be easily portable across TSMC and GF. Moreover I also have my doubts if TSMC N7 6T is sufficient for Rome given the comment from ARM fellow on very low wire speed gain over 16FF+. I think Rome will use N7 HPC 7.5T and aim for max turbo clocks of 3.6 Ghz.

GF HPC likely won't be used by AMD. At least not for any server dies. If they've got a separate desktop die they might.

 

[raghu78]

GF HPC likely won't be used by AMD. At least not for any server dies. If they've got a separate desktop die they might.

I do not think GF 7SoC 6T can clock 4.5+ Ghz. I am quite sure AMD has higher frequency targets for 7nm Ryzen than 12LP based Pinnacle Ridge and 7HPC should fit their needs well. For servers I am pretty confident that AMD is going with TSMC N7 HPC 7.5T given the fact AMD will be sampling 7nm Rome to server customers by the end of 2018.

 

[moinmoin]

Lisa said they'll come to market with whichever fab is ready first. For that to be the case they'd need to already have designs taped out at both fabs.
You grossly overestimate the cost of taping out new dies and underestimate AMD's ability to get it done.

Yes optimization is a major concern, but the cost to do it on both is worth it if it means you minimize TTM risks on arguably your most important product in years. 7nm EPYC will be as its name implies if Intel doesn't get their 10nm sorted, and so far things aren't looking positive on that end. And even if they do get it sorted, 7nm EPYC still has a very good chance to be a performance crown design.

Indeed. This approach works well with keeping the numbers of die designs at a minimum like they did with Zeppelin. With Zen 2 instead more dies we may see two near equal dies taped out at GloFo and TSMC that have foundry specific characteristics and are used accordingly.

 

[Abwx]

...

 

[Topweasel]

Indeed. This approach works well with keeping the numbers of die designs at a minimum like they did with Zeppelin. With Zen 2 instead more dies we may see two near equal dies taped out at GloFo and TSMC that have foundry specific characteristics and are used accordingly.

That might make sense. Use the same basic Die for both factories but dedicate Glofo for desktop die (Ryzen/Ryzen APU) where sales are more predictable and variance easier to deal with. Then TSMC for dies for TR and EPYC. Where they can change their demand as sales grow or shrink.

 

[maddie]

If they have two Zen 2 die mask sets for both GloFlo and TSMC, would that not cause an issue with operational specs? Is it realistic to expect similar characteristics from both fabs?

I am wondering how AMD will be able to supply a standard product with one set of performance and power efficiency values if this happens.

 

[raghu78]

If they have two Zen 2 die mask sets for both GloFlo and TSMC, would that not cause an issue with operational specs? Is it realistic to expect similar characteristics from both fabs?

I am wondering how AMD will be able to supply a standard product with one set of performance and power efficiency values if this happens.

I do not expect AMD to use both TSMC and GF for the same product. 7nm Rome is based at TSMC as AMD already has first silicon. GF will tapeout their first 7nm AMD chip in H2 2018. I expect that to be the Ryzen die. So Vega 7nm , Zen 2 Rome and Navi are at TSMC. Ryzen CPUs and APUs are at GF.

 

[PeterScott]

Lisa said they'll come to market with whichever fab is ready first. For that to be the case they'd need to already have designs taped out at both fabs.
You grossly overestimate the cost of taping out new dies and underestimate AMD's ability to get it done.

Depends what you mean by taped out? Electronic files created and sent? That is done first by AMD, and doesn't incur external costs.

But Full masking layers done by foundry? VERY expensive external cost. Estimates I have seen for masking layers at 7nm were over $100 Million for a single design. It's been going up almost exponentially at each process shrink.

Doing this twice to put the same design at two different foundries, is something to be avoided unless one foundry can't meet volume requirements.

It makes a lot more sense that AMD will put some designs at TSMC and some at GF (They have GPUs/CPU/APU to choose from), but not the same design at both foundries. Greatly increased up front cost for little gain.

 

[jpiniero]

Doing this twice to put the same design at two different foundries, is something to be avoided unless one foundry can't meet volume requirements.

This is true, but it sounds like GloFo is bending over backwards to make it easier/cheaper for AMD to port back over.

If they have two Zen 2 die mask sets for both GloFlo and TSMC, would that not cause an issue with operational specs? Is it realistic to expect similar characteristics from both fabs?

As long as the chips meets the specs it would be fine, and there's a lot that could be done to account for the differences with binning/specific SKUs.

 

[moinmoin]

If they have two Zen 2 die mask sets for both GloFlo and TSMC, would that not cause an issue with operational specs? Is it realistic to expect similar characteristics from both fabs?

I am wondering how AMD will be able to supply a standard product with one set of performance and power efficiency values if this happens.

With every new node at the bleeding edge the exact characteristics are at first totally up in the air as Intel's neverending 10nm story should teach us. And for AMD, aside second sourcing for obvious reasons, this is exactly the reason to go for the same design at to different fabs: This gives them redundancy in the case one of them doesn't turn out as expected. Just like the built in redundancy relying their whole product portfolio (except APUs) on a single die allowed them to increase yield and re-purpose partly faulty dies for lower end chips, having the same design from two fabs would allow them to use the more fitting die characteristics for the more fitting markets and not scramble with unfitting dies with unfitting characteristics.

 

[maddie]

I do not expect AMD to use both TSMC and GF for the same product. 7nm Rome is based at TSMC as AMD already has first silicon. GF will tapeout their first 7nm AMD chip in H2 2018. I expect that to be the Ryzen die. So Vega 7nm , Zen 2 Rome and Navi are at TSMC. Ryzen CPUs and APUs are at GF.

This appears the most reasonable of the suggestions.

Rome, AKA Zen 2, fabbed at TSMC for the EPYC line.
Rome also fabbed at GloFlo for the Ryzen line.

This allows each separate grouping of products to be internally consistent, performance wise, and still allows the flexibility to switch fabs in the case of some catastrophic event.

Imagine the scenario if we have Ryzen 3rd iteration with die from 2 fabs with different overclocking characteristics? Some guys would be on an eternal quest.

 

[PeterScott]

This appears the most reasonable of the suggestions.

Rome, AKA Zen 2, fabbed at TSMC for the EPYC line.
Rome also fabbed at GloFlo for the Ryzen line.

This allows each separate grouping of products to be internally consistent, performance wise, and still allows the flexibility to switch fabs in the case of some catastrophic event.

Imagine the scenario if we have Ryzen 3rd iteration with die from 2 fabs with different overclocking characteristics? Some guys would be on an eternal quest.

No, the most reasonable outcome is that they will pick one fab, for each die design. IMO there is less than 1% chance they will have the same design being built at different foundries (TSMC and GF).

What they could do is something like this:

Zen 2 Ryzen CPU at TSMC.
Zen 2 based APU at GF
GPU top model at TSMC
GPU middle/low end models at GF.

That is the most likely way they will split between Fabs.

 

[VirtualLarry]

IMO there is less than 1% chance they will have the same design being built at different foundries (TSMC and GF).

Didn't they do that for their last high-demand CPU/APU, the Brazos family of chips? I thought that they had some made at TSMC, and some at GF, and that they had slightly different binning / performance characteristics, and therefore some of them were made into desktop chips, and some mobile?

 

[PeterScott]

Didn't they do that for their last high-demand CPU/APU, the Brazos family of chips? I thought that they had some made at TSMC, and some at GF, and that they had slightly different binning / performance characteristics, and therefore some of them were made into desktop chips, and some mobile?

Not that I am aware of, and even if it were true, the exponential cost of masks for each process shrink makes what was affordable a couple of generations ago, prohibitive today. Oddly I can't find the Interview on AT, even though it is credited to AT, but Lisa Su basicially said each fab would get different products:

https://www.anandtech.com/show/1231...n-exclusive-interview-with-dr-lisa-su-amd-ceo

Lisa Su: "So in 7nm, we will use both TSMC and GlobalFoundries. We are working closely with both foundry partners, and will have different product lines for each. I am very confident that the process technology will be stable and capable for what we’re trying to do."

Edit: Link updated to AT link. Thanks to Dayman.

 

[Dayman1225]

Oddly I can't find the Interview on AT, even though it is credited to AT

https://www.anandtech.com/show/1231...n-exclusive-interview-with-dr-lisa-su-amd-ceo

 

[raghu78]

No, the most reasonable outcome is that they will pick one fab, for each die design. IMO there is less than 1% chance they will have the same design being built at different foundries (TSMC and GF).

What they could do is something like this:

Zen 2 Ryzen CPU at TSMC.
Zen 2 based APU at GF
GPU top model at TSMC
GPU middle/low end models at GF.

That is the most likely way they will split between Fabs.

Not that I am aware of, and even if it were true, the exponential cost of masks for each process shrink makes what was affordable a couple of generations ago, prohibitive today. Oddly I can't find the Interview on AT, even though it is credited to AT, but Lisa Su basicially said each fab would get different products:

https://www.anandtech.com/show/1231...n-exclusive-interview-with-dr-lisa-su-amd-ceo

Lisa Su: "So in 7nm, we will use both TSMC and GlobalFoundries. We are working closely with both foundry partners, and will have different product lines for each. I am very confident that the process technology will be stable and capable for what we’re trying to do."

Edit: Link updated to AT link. Thanks to Dayman.

You are assuming that 7nm Rome and 7nm Ryzen use the same die. I think AMD will split their designs at 7nm for server and desktop CPUs. This way AMD can optimize for power efficiency and cost for Rome while optimizing Ryzen for frequency and maximum single thread performance. At 14nm AMD were resource constrained and went with a single source for all designs which was GF. They also kept the number of designs down to 5 for cost reasons - Zeppelin, Raven Ridge, Polaris 10, Polaris 12 and Vega 10.

Anyway I do not see the same design being manufactured at both TSMC and GF. So if its a single die for Rome and Ryzen then all CPUs will be at TSMC. If there are separate dies for Rome and Ryzen then Rome is at TSMC and Ryzen is at GF.

btw Navi is at TSMC 7nm and I do not see GF producing 7nm GPUs. I think GF is going to produce 7nm Ryzen CPUs and APUs.

 

[Abwx]

https://www.computerbase.de/2018-06/amd-ryzen-threadripper-2990x-handel/

 

[Markfw]

Now if I could only figure out how to translate that page.

 

[french toast]

I hope that is placeholder info, if not it's a bad fake.
If it is true, intel has had it in HEDT.

 

[moinmoin]

That Cyberport page is still up: https://www.cyberport.de/gaming/gam...32x-3-4-boost-4-0-ghz-sockel-tr4-cpu-box.html

Some of the data is definitely placeholder (like 180 Watt), but I guess they'll keep the price Amazon style (i.e. honor the price if it turns out higher, lower it should it be lower).

 

[dnavas]

That Cyberport page is still up: https://www.cyberport.de/gaming/gam...32x-3-4-boost-4-0-ghz-sockel-tr4-cpu-box.html

Yeah, but

12nm
250 Watt TDP
Features:
16 Kerne und 32 Threads für blitzschnelle kreative Workloads.

You sure they're talking about a 2990?
With 16 cores?