AMD Ryzen Gen 2 Set For Q2 2018

[The Stilt]

Quick question; does anyone have any information on whether the RR die has the "full" 8MB L3 cache? Mobile RR only has 4MB L3, so if there is only 4MB physically present, that might be the differentiation between SR/PR-based and RR-based R3/5s?

4MB physically in the CCX.

 

[Justinbaileyman]

Is Ryzen Gen 2 going to be consisting of r7 2800x being a replacement for the r7 1800x? Also is it going to be drop in compatible with x370 motherboards or are they going to be releasing new mobo's and chipsets? Last question will be, what is the core count looking like for the r7 2800x?

 

[Dayman1225]

Is Ryzen Gen 2 going to be consisting of r7 2800x being a replacement for the r7 1800x?

Yes

Also is it going to be drop in compatible with x370 motherboards or are they going to be releasing new mobo's and chipsets?

Both apparently

Last question will be, what is the core count looking like for the r7 2800x?

8

 

[Justinbaileyman]

Yes

Both apparently

8

Thanks for the super fast reply. Jeeze only 8 cores still? Hope they bump up the clock speed a tad bit then. Would really like to see 4ghz base with something like 4.5-4.6Ghz boost.

 

[Abwx]

There s far more DT dedicated dies that are sold comparatively to Epyc ones, and DT is not only 30-35% of the PC market but a iGPU less CPU has even smaller TAM...

At the end it makes no sense to release a DT Ryzen replacement before releasing DT APUs, moreover if it s not supposed to be used as server part, most logical is that Ryzen Gen 2 is just the mobile part adapted to DT thanks to a 65W TDP, Pinnacle Ridge that would not be used for servers would be almost pointless.

 

[Topweasel]

Thanks for the super fast reply. Jeeze only 8 cores still? Hope they bump up the clock speed a tad bit then. Would really like to see 4ghz base with something like 4.5-4.6Ghz boost.

Zen + was always just going to be a performance uplift with a few tweaks and newish process. Current running theory is that at a minimum Ryzen 3k (Zen 2.0) will be at least 12 cores.

But you are in luck Base clocks and all core turbos should be getting to and maybe slightly over 4GHz with some room for overclocking. The process is going to be made for high clock speeds and even if we are going to be limited in the power envelope for stock clocks, it should have a lot more breathing room for overclocks.

 

[geoxile]

Thanks for the super fast reply. Jeeze only 8 cores still? Hope they bump up the clock speed a tad bit then. Would really like to see 4ghz base with something like 4.5-4.6Ghz boost.

The 12nm process promises +10% over leading 16nm and 14nm so we should see about those speeds for the 1800x equivalent. Maybe more from high level optimizations.

 

[amd6502]

Is Ryzen Gen 2 going to be consisting of r7 2800x being a replacement for the r7 1800x? Also is it going to be drop in compatible with x370 motherboards or are they going to be releasing new mobo's and chipsets? Last question will be, what is the core count looking like for the r7 2800x?

I thought Raven Ridge APU and CPU derivatives would be 2000 series.

Pinnacle Ridge would be 3000 series, or so I assume. Core count should be the same. Same basically except manufactured at 12nm, presumably with improved stepping and maybe server uncore improvements.

The 12nm process promises +10% over leading 16nm and 14nm so we should see about those speeds for the 1800x equivalent. Maybe more from high level optimizations.

I think 10% is optimistic, but perhaps it will be almost 10%. Summit ridge was agressively binned to get to 4ghz. Often perfectly fine cores were disabled just because they couldn't clock quite high enough.

 

[Topweasel]

I thought Raven Ridge APU and CPU derivatives would be 2000 series.

Pinnacle Ridge would be 3000 series, or so I assume. Core count should be the same. Same basically except manufactured at 12nm, presumably with improved stepping and maybe server uncore improvements.



I think 10% is optimistic, but perhaps it will be almost 10%. Summit ridge was agressively binned to get to 4ghz. Often perfectly fine cores were disabled just because they couldn't clock quite high enough.

Nope both RR and PR will both be 2k series.

 

[The Stilt]

The 12nm process promises +10% over leading 16nm and 14nm so we should see about those speeds for the 1800x equivalent. Maybe more from high level optimizations.

It does, but at ISO power.
Meaning that promise can be fullfilled by allowing e.g. 3.3GHz at the same power 14nm LPP part consumed at 3GHz.
It doesn't necessarily mean that the process itself can clock any higher than it's predecessor. Hopefully it will thou (and significantly more than 10%), since AMD will essentially live or "die" by the fact.

 

[HurleyBird]

Thanks for the super fast reply. Jeeze only 8 cores still?

He doesn't know that. Some people on this forum have a bad habit of conveying the most plausible scenario as fact.

I'd put the odds of AMD upping the core count to 12 at about 15%, but that's just an educated guess.

 

[Dayman1225]

He doesn't know that. Some people on this forum have a bad habit of conveying the most plausible scenario as fact.

I'd put the odds of AMD upping the core count to 12 at about 15%, but that's just an educated guess.

¯\_(ツ)_/¯

 

[HurleyBird]

Old road maps aren't necessarily infallible. Later road maps stopped listing the number of cores/threads, perhaps for a reason. The old roadmap also strongly suggested that Pinnacle Ridge wouldn't receive a new chipset, which now we know isn't the case.

Now, I'm not saying that going above 8 cores is likely at all, merely that it isn't a certainty.

 

[Topweasel]

Old road maps aren't necessarily infallible. Later road maps stopped listing the number of cores/threads, perhaps for a reason. The old roadmap also strongly suggested that Pinnacle Ridge wouldn't receive a new chipset, which now we know isn't the case.

Now, I'm not saying that going above 8 cores is likely at all, merely that it isn't a certainty.

The bottom is a lot more recent. But the key point is development takes awhile. AMD's module system takes months off of the drawing-board point. But all sort of sampling, spinning out, tweaking, taping out, process testing, binning, qualify, validating, and changing over production means there is still almost a 3 year development cycle from original planning to shipping to retail. The decisions on what Pinnacle Ridge will be happened a long time ago and AMD isn't going change to much from when they originally put it out on the road map.

The only reasons why we got more cores on Intel's X299 was made possible by Intel using a re-purposed platform for X299 so they just used another chip that was developed for the original socket and just tested for the increased power and clock speed. Normally something like that can't happen on a whim. So no AMD isn't changing that much on Pinnacle Ridge.

 

[HurleyBird]

The bottom is a lot more recent.

The number of cores/threads for Pinnacle Ridge is also absent in the bottom image. I do agree with all of your points which is why I think that 8C/16T is by far the most likely scenario. But not to the point where I'd say it's necessarily a certainty.

 

[Topweasel]

The number of cores/threads for Pinnacle Ridge is also absent in the bottom image. I do agree with all of your points which is why I think that 8C/16T is by far the most likely scenario. But not to the point where I'd say it's necessarily a certainty.

It says performance uplift which screams process change. There is another slide that came out between them that specifically referred to using Summit Ridge arch, which to us means AMD is saying it's an uplift of Zen and not the die. But if you look at how AMD words things it all but confirms that it is mostly a process switch.

 

[HurleyBird]

But if you look at how AMD words things it all but confirms that it is mostly a process switch.

They also said that Zen progression was going to be "Tock, tock, tock," so a bit of mixed messaging. To qualify as a "tock" Pinnacle ridge might have greater than expect frequency improvement, or a significantly improved uncore. Additional cores would hit that spot as well. Maybe some combination.

Of course, they may have been misleading us with that quote ("IPC increases" and others come to mind), or may just have been overly optimistic. We'll know for sure pretty soon

 

[tential]

It's insane to expect a core increase.
From the design of the core, it's most efficient to do it like this it not?
This was the REASONABLE thing to expect from AMD all along, and we got it. I don't expect to get weird core configurations when we got an extremely logical core/thread lineup from AMD.
AMDs focus needs to PURELY be on optimization now. I'd be quite annoyed if AMD thought that a 10c/20t high end chip would be appropriate for mainstream high end when we clearly need a FASTER cpu. It wouldn't even make sense, I don't even like discussing it any further.

Edit:
The one feature I need from AMD to work, GPU passthrough doesn't work.

 

[raghu78]

They also said that Zen progression was going to be "Tock, tock, tock," so a bit of mixed messaging. To qualify as a "tock" Pinnacle ridge might have greater than expect frequency improvement, or a significantly improved uncore. Additional cores would hit that spot as well. Maybe some combination.

Of course, they may have been misleading us with that quote ("IPC increases" and others come to mind), or may just have been overly optimistic. We'll know for sure pretty soon

I think PR will be a significant improvement in ST perf and MT perf. Here are the changes I expect

1. Ultra High performance libraries with relaxed CPP. My guess is 12LP 10.5T, CPP=84nm .
2. Improved memory controller with higher DDR4 speeds upto 4000 Mhz. Better BIOS optimizations to get the best possible performance.
3. Improved Precision Boost similar to or better than Raven Ridge.
https://www.anandtech.com/show/1196...-apus-for-laptops-with-vega-and-updated-zen/3
4. Memory and cache latency reduction especially L3 cache latency.

I do not expect an increase in core count. I think PR will be designed for 5 Ghz. I think AMD will go for the best possible ST performance and from now on I do not expect AMD to have a common die for server and client. 7nm Rome on GF 7SoC 6T and 7nm Ryzen on 7HPC 9T.

 

[itsmydamnation]

I doubt cache latencies are going to reduce at all. 1 they are already very good, 2 the way caches operate and interrelate to each other, tags, etc is complex and changes have to be done from a holistic point of view. look at CON cores, the fundamental cache performance didn't change in 5 odd years.

Think of this as a doing something as cheap as possible to buy more head room in one target market. More head room ,better firmware , maybe some update IP blocks, better boost implementation (see firmwre). Thats what is realistic to expect.

 

[CatMerc]

I doubt cache latencies are going to reduce at all. 1 they are already very good, 2 the way caches operate and interrelate to each other, tags, etc is complex and changes have to be done from a holistic point of view. look at CON cores, the fundamental cache performance didn't change in 5 odd years.

Think of this as a doing something as cheap as possible to buy more head room in one target market. More head room ,better firmware , maybe some update IP blocks, better boost implementation (see firmwre). Thats what is realistic to expect.

Threadripper, EPYC, and Raven, already have lower L2 latencies and maybe L3.

 

[Thunder 57]

I doubt cache latencies are going to reduce at all. 1 they are already very good, 2 the way caches operate and interrelate to each other, tags, etc is complex and changes have to be done from a holistic point of view. look at CON cores, the fundamental cache performance didn't change in 5 odd years.

Think of this as a doing something as cheap as possible to buy more head room in one target market. More head room ,better firmware , maybe some update IP blocks, better boost implementation (see firmwre). Thats what is realistic to expect.

It's definitely possible. Supposedly RR already has significantly reduced L2 latency: https://mobile.twitter.com/InstLatX64/status/941279542416760833?prefetchTimestamp=1513805844807

Secondly, cache performance did improve in the construction core era, and by a non trivial amount. Piledriver had the same latencies as far as I know, but the point of PD was to get BD's power usage in check, not really go after performance (other than higher clocks due to less power). The first design aimed at doing that was Steamroller, which had better latencies. L2 latency was down slightly, but had much better write performance in particular:

https://www.extremetech.com/computi...roller-digging-deep-into-amds-next-gen-core/2

Keep in mind since there was never going to be a Steamroller with L3, there was nothing they cared to do about it. AMD even said they identified the horrid L3 latency issue, but had no plans to fix it.

So there may be some cache tweaks, but I don't think there will be anything to significant until Zen 2. Unless of course the SR/RR L2 numbers in that tweet are indeed correct. I think IPC increase will be pretty minimal, with most of the gains coming from higher clocks supposedly allowed by 12nm LP.

 

[Topweasel]

It's definitely possible. Supposedly RR already has significantly reduced L2 latency: https://mobile.twitter.com/InstLatX64/status/941279542416760833?prefetchTimestamp=1513805844807

Secondly, cache performance did improve in the construction core era, and by a non trivial amount. Piledriver had the same latencies as far as I know, but the point of PD was to get BD's power usage in check, not really go after performance (other than higher clocks due to less power). The first design aimed at doing that was Steamroller, which had better latencies. L2 latency was down slightly, but had much better write performance in particular:

https://www.extremetech.com/computi...roller-digging-deep-into-amds-next-gen-core/2

Keep in mind since there was never going to be a Steamroller with L3, there was nothing they cared to do about it. AMD even said they identified the horrid L3 latency issue, but had no plans to fix it.

So there may be some cache tweaks, but I don't think there will be anything to significant until Zen 2. Unless of course the SR/RR L2 numbers in that tweet are indeed correct. I think IPC increase will be pretty minimal, with most of the gains coming from higher clocks supposedly allowed by 12nm LP.

17ns to 12ns while an eternity for a CPU isn't a major change. Couldn't this also be caused by the increased complexity and size of 2 1MB slices instead of 1?

 

[Thunder 57]

17ns to 12ns while an eternity for a CPU isn't a major change. Couldn't this also be caused by the increased complexity and size of 2 1MB slices instead of 1?

That's nearly a 30% decrease, which is significant. It is only one (very small) part of the performance equation though. I do think only having to handle one CCX is what made that possible as well, as you suggested. That doesn't mean there isn't room for improvement in SR, though.

 

[Topweasel]

That's nearly a 30% decrease, which is significant. It is only one (very small) part of the performance equation though. I do think only having to handle one CCX is what made that possible as well, as you suggested. That doesn't mean there isn't room for improvement in SR, though.

Like I said it's a big difference in CPU speak but it also is a rather rather small number which means several factors could be impacting it. Specially when you look at how little the L3 changes.