AMD Ryzen (Summit Ridge) Benchmarks Thread (use new thread)

[coercitiv]

AMD demos their product in order to show it's up there with the big boys, people gloss over that realization like it was a given and proceed to nitpick in order to get review like info from a preview like presentation.

I take this opportunity to congratulate AMD management and marketing: Never in the history of AMD have so many enthusiast Intel cores been used to render an AMD CPU logo! Looking forward to product launch, this Achilles better have no weak heel, no arrows will be spared on launch day.

So the future is . . . hyperbolic time chambers?!?

Yes, we'll slow time inside the package.

 

[itsmydamnation]

: Never in the history of AMD have so many enthusiast Intel cores been used to render an AMD CPU logo! .

I actually really LOL'd at that.

 

[psolord]

AMD demos their product in order to show it's up there with the big boys, people gloss over that realization like it was a given and proceed to nitpick in order to get review like info from a preview like presentation.

I take this opportunity to congratulate AMD management and marketing: Never in the history of AMD have so many enthusiast Intel cores been used to render an AMD CPU logo! Looking forward to product launch, this Achilles better have no weak heel, no arrows will be spared on launch day.

That was epic!

 

[CatMerc]

I take this opportunity to congratulate AMD management and marketing: Never in the history of AMD have so many enthusiast Intel cores been used to render an AMD CPU logo!

 

[Atari2600]

Never in the history of AMD have so many enthusiast Intel cores been used to render an AMD CPU logo!

 

[TheELF]

this Achilles better have no weak heel, no arrows will be spared on launch day.

Lisa already stated the heel in the presentation 1/3 (33%) of this at least 40% IPC upscale comes from senseMI,the neural network thingy, which makes it pretty safe to say that it won't work that well on serial code.

 

[CatMerc]

Alright, I attempted to discover what the default sampling rate is, and it appears to be 128.

 

[bjt2]

Lisa already stated the heel in the presentation 1/3 (33%) of this at least 40% IPC upscale comes from senseMI,the neural network thingy, which makes it pretty safe to say that it won't work that well on serial code.

Actually i remember 1/4.
On serial code there is no need of branch prediction, so its efficiency is pointless.

 

[coercitiv]

Lisa already stated the heel in the presentation 1/3 (33%) of this at least 40% IPC upscale comes from senseMI,the neural network thingy

It was one quarter, 25%.

 

[Atari2600]

On serial code there is no need of branch prediction, so its efficiency is pointless.

?!?!?

You want to reword that?

I think a few of you have a major misconception and are equating instruction level parallelism with code level parallelism!

 

[superstition]

Alright, I attempted to discover what the default sampling rate is, and it appears to be 128.

What?

 

[Atari2600]

42

The answer is 42.

 

[cytg111]

Lisa already stated the heel in the presentation 1/3 (33%) of this at least 40% IPC upscale comes from senseMI,the neural network thingy, which makes it pretty safe to say that it won't work that well on serial code.

Isnt that the other way around? Or is my brain wandering again...
These massive parallel workloads ... are parallel in nature (somthing the Itanium would love) and thus dont fail a branch all that often.
I would expect a rendering task to not branch mispredict very often.
Inherent single threaded tasks/code on the other hand....

 

[superstition]

42

The answer is 42.

 

[itsmydamnation]

Lisa already stated the heel in the presentation 1/3 (33%) of this at least 40% IPC upscale comes from senseMI,the neural network thingy, which makes it pretty safe to say that it won't work that well on serial code.

humm so your telling us on the over 40% IPC improvement (funny how you forget that was said by Lisa)
1. advanced prefetching doesn't help serial IPC
2. advanced prediction doesn't help serial IPC
3. and as a result speculative execution doesn't help serial IPC

The Pentium pro called , its telling you that you have been wrong since at least 1995......

 

[superstition]

The Pentium pro called , its telling you that you have been wrong since at least 1995......

"It is the gold standard." — Kevin Bacon

http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...zen-benchmarks.2482739/page-117#post-38630126
https://www.google.com/search?q=pentium+pro+gold&ie=utf-8&oe=utf-8

(Definitely geeking out here a bit.)

 

[cytg111]

What the hell is sensemi anyway? Neural net. Got it. Is it pretrained or is it a supervised learning scenario where it adapts the the current workload? If it is the latter then we just got a JIT(JustInTime) Branch Predictor .. thats kinda cool (if it works)... but riddle me, such a thing can be exploited to perform worse, much worse.

 

[CatMerc]

What?

If you start up Blender and don't change any settings, the sampling rate is 128. This is fairly close to the 140 we speculate they used in the live demo, so it could be in fact 128.

 

[TheELF]

humm so your telling us on the over 40% IPC improvement (funny how you forget that was said by Lisa)
1. advanced prefetching doesn't help serial IPC
2. advanced prediction doesn't help serial IPC
3. and as a result speculative execution doesn't help serial IPC

The Pentium pro called , its telling you that you have been wrong since at least 1995......

I said at least 40% ,how else should I have said it?
IIRC lisa said it will get data ready before the program needs it,is this possible for serial code where the data the program needs is dependent on the immediately previous instruction?

I said serial code not just any single threaded task.

 

[Atari2600]

IIRC lisa said it will get data ready before the program needs it,is this possible for serial code where the data the program needs is dependent on the immediately previous instruction?

YES!

Its commonplace for over 20 years.


At the instruction level, nowadays the CPU never works on the basis of waiting for a single code to pass through the pipe, but instead tries to jump ahead with predictions of what might happen next. If the CPU is right, then it saves time, if its wrong, then the next "step" cannot be fast-tracked.

So, at that level, the line between serial and parallel "code" is very blurry.

 

[bjt2]

?!?!?

You want to reword that?

I think a few of you have a major misconception and are equating instruction level parallelism with code level parallelism!

What do you mean by serial code then? By serial code i mean branchless code, maybe with conditional instructions (actual only move there exist in x86).
If by serial code you mean code with a lot of dependencies between instructions, so with much stalls, i don't see why the branch prediction might suffer...

 

[Nothingness]

On serial code there is no need of branch prediction, so its efficiency is pointless.

Huh? Branch prediction is one of the most important things for single thread lack of performance: no matter how wide your machine is, if you get branch prediction wrong, you'll be flushing loads of instructions and leave a lot of performance on the table. I guess you meant something else.

EDIT: just saw your post above
In that context, I'd say sequential code rather than serial for branchless code.

 

[bjt2]

I said at least 40% ,how else should I have said it?
IIRC lisa said it will get data ready before the program needs it,is this possible for serial code where the data the program needs is dependent on the immediately previous instruction?

I said serial code not just any single threaded task.

Serial code ran just once? Unless you have a gigabyte or more of code, without jumps and loops, the performance hit will be negligible... And no CPU on earth can predict well a new instruction flux...

 

[Atari2600]

What do you mean by serial code then? By serial code i mean branchless code, maybe with conditional instructions (actual only move there exist in x86).
If by serial code you mean code with a lot of dependencies between instructions, so with much stalls, i don't see why the branch prediction might suffer...

Serial code is code with a single thread in the language its written in.

But that is not a code without branches. Do you write much code without any if-else statements? Or what about for or while loops?

 

[witeken]

About the hilarious TDP discussion.

Zen idle: 93W
Intel idle: 106W

Zen load: 187W
Intel load: 191W

Zen delta: 94W
Intel delta: 85W

So tell me, who has the highest performance per watt?