That assumption is incorrect.
AMD has stated 40% IPC improvement over a Excavator core from the day one, and according to AMD a single module is two cores on every 15h design.
With that 40 % improvement, does AMD mean integer performance or floating point performance ?
Because with multithreaded software relying heavy on the floating point unit, would it not be easy when compared to the current CMT design with only one FPU per module/2 cores?
With that 40 % improvement, does AMD mean integer performance or floating point performance ?
Because with multithreaded software relying heavy on the floating point unit, would it not be easy when compared to the current CMT design with only one FPU per module/2 cores?
No it doesn't, only a handful of consumer apps benefit from quad channel memory. I doubt they're even in the double digits (the more popular ones) & even then high speed DDR4 in dual channel is much preferred because of stability & the fact that there aren't too many CPU's which can handle 4GHz quad channel memory, or make better use of it.
And for Phenom? For Bulldozer?In the past (with PD, SR, XV) the quoted IPC improvement has been very close to the average figure, which naturally includes both integer and floating point workloads. For Steamroller the official average figure was 10% and for Excavator 5%. Both of them can achieve higher and lower numbers depending on the workload, but these figures are extremely close to the average.
And for Phenom? For Bulldozer?
They're the new uarchs of relevance.
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(Opinions are own)
Performance compares for AMD with ANY major uarch+process change have always turned out fallacious. Just when they've been boasting about it for 5 years in the making and just when it counted most. Just when the change was so drastic. From memory:No idea.
What difference does it make to the way AMD evaluates the IPC if it is a brand new µarch or a evolution version of existing one?
They never said anything about IPC when it came to bulldozer, in fact they were point blank asked multiple times and have always avoided to answer that question. We all just assumed it was going to be better than previous gen (Phenom II), because that's been their historical norm.Bulldozer - they said same IPC but much higher frequencies.
Zen has 2x ALU and 2x FP resources per core Vs Excavator design. This should mean that one Zen core running 2 threads on FP co processor should roughly match one whole EX module running 2 threads on its own FP co processor. There is also a factor of lower FP instruction latencies that Zen supposedly has Vs EX so this also should play a big role in fp performance of Zen.
In the past (with PD, SR, XV) the quoted IPC improvement has been very close to the average figure, which naturally includes both integer and floating point workloads. For Steamroller the official average figure was 10% and for Excavator 5%. Both of them can achieve higher and lower numbers depending on the workload, but these figures are extremely close to the average.
With that 40 % improvement, does AMD mean integer performance or floating point performance ?
Because with multithreaded software relying heavy on the floating point unit, would it not be easy when compared to the current CMT design with only one FPU per module/2 cores?
Let's instead try an objective analysis, while there are still some facts missing for a final result.Performance compares for AMD with ANY major uarch+process change have always turned out fallacious. Just when they've been boasting about it for 5 years in the making and just when it counted most. Just when the change was so drastic. From memory:
Bulldozer - they said same IPC but much higher frequencies.
Neither was true. And Thuban was far faster, IPC wise.
Barcelona - they compared a simulated 2.6GHz model in SPEC rate and said AMD is 42% faster than the fastest Intel Xeon.
9 months on they could only launch with 2GHz... while Clovertown 3.16GHz 45nm was now shipping, along with Tigerton. And Penryn slapped Agena around in every department. Don't even mention the TLB bug, dead clocking or the paper launch.
Oh, that 40% figure again.
http://www.cnet.com/news/a-dazed-intel-shifts-into-comeback-mode/"(On) average, we are 40 percent-plus better than the competition in performance and a little bit better in power, and the combination is 1.5X in terms of power/performance," said Pat Gelsinger
It's just a puzzle game. As you see, we still have to wait for Hot Chips to fill in some speculative holes.Very interesting.
Do you know, which frequency the K10 and Clovertown used for the comparison had? Finally, when Barcelona launched at max. 2GHz in September 2007, Intel already had 3GHz Clovertowns.
Yes, this 40% figure never can be true.
Intel's own marketing material seems to admit that a Xeon E5472 (Edit : 3GHz..) with 800MHz memory is just as a fast as AMD's quad-core at 2GHz. AMD's 2.5GHz model will surely take the lead in LS-DYNA. Looking at the Fluent and LS-DYNA benchmarks it appears that AMD will remain very competitive in the HPC market.
Yea let's talk about stuff no one remembersWith "ANY" do you also mean 486->K5, K5->K6->K6-2->K6-3, K6-3->K7, etc.?
Also see the reviews as to what AMD told reviewers too. Look at Anand himself, similar IPC:AMD officially (not in forums by a non-engineer) said about IPC:
"without significant loss on serial single-threaded workload components", which could mean IPC(BD) < IPC(K10) by 0 to 5% on average.
It wasn't true at all. Barcelona nor Agena were any where near their counterparts at launch. Not in performance, not in power, not in clocks and no way in underclocking/overclocking.Regarding Barcelona:
This is probably a plans vs. process reality thing. When they looked at results at simulated or even "OC'ed" 2.6GHz (ES could probably run that fast, just at too high power/voltage for short times), there were 2.66GHz Clovertowns reviewed just weeks before Allen's interview. Aside from that model, the next slower one had 1.86GHz only. What did they use?
http://ark.intel.com/de/products/codename/23349/Clovertown#@All
Do you know, which frequency the K10 and Clovertown used for the comparison had? Finally, when Barcelona launched at max. 2GHz in September 2007, Intel already had 3GHz Clovertowns. That would mean an performance projection delta of -32% (compared to 2.6GHz K10 vs. 2.66GHz CT).
Yes, this 40% figure never can be true.
It wasn't true at all. Barcelona nor Agena were any where near their counterparts at launch. Not in performance, not in power, not in clocks and no way in underclocking/overclocking.
I can keep naming things that are all headed in the direction of improved IPC, So start naming things other then "derp derp AMD" that look like performance limiters..............
I personally don't care for IPC alone.Everyone ignores that a server guy said it, on anything greater the 1P amd still ruled to roost until Nehalem.
But again i ask the doubters, where is the performance deficit coming from, which area's specifically. I would never try to guess IPC with the known information,but you guys have no problem doing so. But there is nothing in all the known detail ( we know quite a bit from link'din, die shot, compiler patches and what amd released a few days ago) thats says IPC can't be high.
More execution width
Lower latency cache
More associative, larger per int core L1I
more cache bandwidth
larger PRF's
greater issue width (u-op cache)
I can keep naming things that are all headed in the direction of improved IPC, So start naming things other then "derp derp AMD" that look like performance limiters..............
I did a quick test and now I'm even more confused about AMDs claims. If the results AMD displayed versus Broadwell-E are fair and real then it is obviously great, however potentially there is a huge risk this back firing... I used the newest public pre-compiled Blender build (2.77a 64-bit) and ran the standard "BMW27" (ver. 4) benchmark scene. I reduced the scene size to 320x180 pixels to bring down the rendering time with a single thread to sane levels, and set the tile size to 20x20 pixels (even tiles, similar to Cinebench and AMD's own Blender demo). Piledriver operating at 3.5GHz completed the scene in 6 minutes 49 seconds. The score was within 200ms regardless if the CMT was enabled or disabled. Meanwhile my Haswell-EP operating at the same 3.5GHz frequency completed the scene 2 minutes 57 seconds. That's 131% higher IPC for Haswell-E. Since Broadwell-E should be < 10% faster than Haswell-E, AMD basically claims that they've achieved > 140% IPC improvement over Piledriver with Zen
I still need to test if using dual channel instead of quad or downcoring some of the L3 cache on Haswell-EP makes a major difference.
When you think about it, Zen has 2x the FP and L/S resources per core Vs PD and since it has 2x more threads that comes to around same amount of resources per thread (with supposedly lower instruction latencies). Also it has SMT which adds another 20-30% if done right. Should be just about 130% faster than PD.
How does SMT have anything to do with what I just wrote?
Alternatively one could ask how the average IPC improvement becomes just 40% if they manage to hit over 140% in some cases?
I did a quick test and now I'm even more confused about AMDs claims. If the results AMD displayed versus Broadwell-E are fair and real then it is obviously great, however potentially there is a huge risk this back firing... I used the newest public pre-compiled Blender build (2.77a 64-bit) and ran the standard "BMW27" (ver. 4) benchmark scene. I reduced the scene size to 320x180 pixels to bring down the rendering time with a single thread to sane levels, and set the tile size to 20x20 pixels (even tiles, similar to Cinebench and AMD's own Blender demo). Piledriver operating at 3.5GHz completed the scene in 6 minutes 49 seconds. The score was within 200ms regardless if the CMT was enabled or disabled. Meanwhile my Haswell-EP operating at the same 3.5GHz frequency completed the scene 2 minutes 57 seconds. That's 131% higher IPC for Haswell-E. Since Broadwell-E should be < 10% faster than Haswell-E, AMD basically claims that they've achieved > 140% IPC improvement over Piledriver with Zen
I still need to test if using dual channel instead of quad or downcoring some of the L3 cache on Haswell-EP makes a major difference.
BTW I thought it was settled that 40% figure was over EX core. EX core is not the same as PD and you wrote about it above. So 40% above EX is around ~60% above PD (or so, depending on the workload of course).