CPCHardware said:Strange point concerning Ryzen: "XFR" only appears in the marketing docs and never in the technical docs...
The Buddhists are probably pleased more than anything else.
Hmm . . . that could work. L3 is per CCX, right? What if they're using something like a modernized version of HT Assist to mitigate inter-CCX communication problems? We might not detect it unless using something with a sufficiently-large data set.
Can you get a dual socket board for $300?
Oh, and the 2620v4 has a base frequency of 2.1GHz. Kinda changes the perspective your putting on things.
while ( (boostFlags & BOOST_ENABLED) == BOOST_ENABLED ) {
float turboMaxMult = gTurboMaxMult;
float maxCorePower = gMaxCorePower;
float maxTDP = gMaxTDP;
float maxVolts = gMaxVolts;
// Extended Frequency Range (XFR)
if ( (boostFlags & XFR_ENABLED) == XFR_ENABLED ) {
XFRConfigRef xfr;
turboMaxMult = xfr.maxMultiplier;
maxCorePower = xfr.maxCorePower;
maxTDP = xfr.maxTDP;
maxVolts = xfr.maxVolts;
}
// ... Precision Boost logic follows ...
}The problem is as long as engine and games have a DX11 code path the game and engine inherently are limited by DX11 paradigms which is 1 thread for draw calls. Tacking on dx12 on an engine based probably on dx9 (or even older) won't give great benefits especially not scaling well to an 8-core. So the whole tool-chain from engine to game has to be made from scratch. That will take years and then you can upgrade again.
Besides that, some games even in 2017 are 100% ST dependent, prime exampel being starcraft 2. So If you play that alot, 7700k is the way to go.
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Media "guru" bullshit.
By-and-by large, the clueless will buy:
- a Ryzen because their mate who knows something about computers said its the one to get* // there is someone in the shop who actually knows a bit and cares about getting their customers' the best bang for buck*.
- an Intel because that is what they've always done // that is what the even more gormless idiot in the shop said to get // 'cos they've heard of Intel.
The educated will buy:
- the CPU that best meets their needs and can properly evaluate their needs.
None will buy based on the colour of the box.
*Assuming Zen delivers the performance we are kinda expecting at this point at the prices we hope for.
Media "guru" bullshit.
By-and-by large, the clueless will buy:
- a Ryzen because their mate who knows something about computers said its the one to get* // there is someone in the shop who actually knows a bit and cares about getting their customers' the best bang for buck*.
- an Intel because that is what they've always done // that is what the even more gormless idiot in the shop said to get // 'cos they've heard of Intel.
The educated will buy:
- the CPU that best meets their needs and can properly evaluate their needs.
None will buy based on the colour of the box.
*Assuming Zen delivers the performance we are kinda expecting at this point at the prices we hope for.
I'd say they're more likely to be content with it than pleased. I mean... they're Buddhists.
L3 is per CCX, yes.
I know some of how the inter-CCX communications might work, based on the die shots, the CCX design, and some comments by AMD personnel.
I see two possibilities - the first is that there is NO inter-CCX communication and it is all done through the memory controller... this would be the slowest method and would be a very bad idea.. it would result in horrible multi-threaded scaling issues... which we simply aren't seeing at all with the leaks...
The second is an external clone of the internal L3 tags. Each CCX would have an external L3 tag set to which it can write, but not read. When a CCX misses on its own cache it sends a request out on its high-speed, low latency, external command bus to a specific memory controller. The memory controller would scan the L3 tag cache which clones the other CCX's tags, letting it know if the data is on-die, but just in the other L3...
If the tag is in the other L3, it will make a request for that data from the other CCX and that data will be tagged for the other CCX & core and sent on the wide, high speed, inter-CCX data bus (which resides in an upper metal layer).
As the servicing L3 would not need to do an L3 lookup, you save a cycle or two, which pays for some of the round-trip costs. The extra cost would only be a couple nanoseconds of latency - compared to 20+ for going to main memory - with double the bandwidth (100GB/s vs 50GB/s).
In addition to all of that, there needs to be some method of synchronizing shared data reliably. I'm very surprised by the layout of the CCXes - I would have thought the L3 caches butting against each other would have made for easier and faster communications, but it seems each CCX has its own preferred memory channel which may have an attached global L3 tag clone set.
It would be efficient enough, but would cost quite a bit of area outside of the CCX...
It will be REALLY interesting to see what route AMD took (I expect we will get some solid details on this with the launch-day reviews).
I wonder how much the Infinity Fabric interconnect can affect inter-CCX communication. It would make sense for them to develop it to handle such communications to further scale into the 32-core server beasts they're talking about later on, why invent the wheel twice?
Yeah, it being in Vega is probably half the reason why we're not seeing Raven Ridge until after Vega launch.Infinity fabric is the command bus and data bus in my post
It just extends off the chip. In theory, it should allow only minimal extra penalty for going to the other die over going to the adjacent CCX on the same die.
Jim Keller was basically the king of high-performance NUMA back in the day... only makes sense he's advanced since then and included that in Zen.
What's more interesting is that I think this same tech is also now in Vega ;-)
You are free to believe what you want, but marketing is not BS.
The poster I quoted stated that even if Ryzen has Haswell IPC, it's not impressive because it's on the level of a 4-year old chip, rather than dealing with performance metrics, the only thing that matters, now it's age. It's textbook spin.AFAIK we've got a 250-page thread of spin with nothing more than a set of benchmarks from AMD that can't yet be verified by the review sites and anyone who chooses to. If I'm correct, no amount of guesswork, wishful thinking, logic and rationalisation changes that. "Leaks" aren't verifiable either so they have even less credibility than AMD's own benchmarks.
I sincerely hope that AMD has produced a viable set of competitors to Intel's current range (as it would shake up the market), even if it wasn't at all price points, however until we have some publicly verifiable benchmarks, speculation is simply a waste of time, and criticising speculation that doesn't agree with your own opinions an even bigger waste of time.
lol
AMD Ryzen Hype Ships
Original song : Conquest Of Paradise by Vagelis
Yeah, it being in Vega is probably half the reason why we're not seeing Raven Ridge until after Vega launch.
If they're using a Vega based design for the APU, then the IF being present will potentially be a huge performance boon.
I didn't feel the same for say, the RX 480, either because the leaks and demos were unimpressive (or at the very least, not in line with the hype we saw at the time). What we got was pretty much in line with what was demoed and leaked, too. Everything except the lack of power efficiency, which took me by surprise.
Did you catch the term "directory based" (like good old HT Assist) somewhere? It's been mentioned on several LinkedIn profiles.The second is an external clone of the internal L3 tags. Each CCX would have an external L3 tag set to which it can write, but not read. When a CCX misses on its own cache it sends a request out on its high-speed, low latency, external command bus to a specific memory controller. The memory controller would scan the L3 tag cache which clones the other CCX's tags, letting it know if the data is on-die, but just in the other L3...
It's actually very efficient. AMD overvolted the efficiency right out of it.
At stock voltage my GPU pulls 110W and throttles. Stock is at 1.15V... I can use 1.05V completely safely - zero issues to date (it can actually go to 1035V, but I like headroom). It now uses only 80W and stays solid at 1288MHz (XFX RX 480 GTR 8GB stock turbo).
In fact, at 1.05V, I can hit a little over 1.3Ghz. At 1.15V I can get nearly to 1.4GHz, where I hit a wall even 1.3V can't get me past.
I would be surprised if Zen behaved any differently - and is any more relatively efficient... should be a tuner's dream
I never said marketing was BS. Its extremely important.
But the colour of the box of a retail CPU is sooo irrelevant its unreal.
Q: Who buys CPUs in retail boxes?
A: Someone building a system.
Q: Where do the majority get their CPUs?
A: Online. Where you don't even see the box.
Q: Does someone who is building their own system (or a system for others) tend to know what they are doing or get advice from those that do?
A: Yes.
Q: Will that person then be walking into the store knowing what is compatible with their current system, or walking in with a few options in mind which will have been considered beforehand?
A: Very likely. Too many possible incompatibilities and permutations to risk a buy without some forethought.
Q: Will the clueless who may be enticed by a "oohhh shiny" buy a CPU in a fancy retail box?
A: No, they are infinitely more likely to be buying a finished box instead.
Every GPU that is slated for 2017 release, not re-release is going to have features from Greenland GPU.Did you catch the term "directory based" (like good old HT Assist) somewhere? It's been mentioned on several LinkedIn profiles.
And CCXs + DMCs + FCH might all simply be connected via the NOC mesh. How could it look like with 4 remaining links going off the die?
Vega certainly has it, at least as Greenland on Snowy Owl:
Well, don't we sort of know that Zen's die is quite a bit larger than just 2 CCXs?It would be efficient enough, but would cost quite a bit of area outside of the CCX...
Making a statements based on the binned top tier rx480 does not help your cause, though. What we really know is that at least first batches of rx480 had ridiculous variance, ranging from bearable to madly throttling.It's actually very efficient. AMD overvolted the efficiency right out of it.
Okay, that is the viable explanation, i am dumping my pessimist version.XFR is just a switch that allows Precision Boost's top turbo bin to be ignored. There's nothing really technical about it to say.
Should fit about 10CUs and 8 RoPs... In line with last RR rumors, too.But a 44mm^2 GPU would be epic...
Again, you might feel that way, but its brand management, which happens to be something AMD needs a lot.
There is a reason why Coca Cola has a bunch of different versions of its logo on its collateral. To you, the logo is a logo. To marketing people, the logo is an emotional trigger.
I would assume you have no experience in CPG marketing. You personally may not be influenced by it, but many are. To build a brand, you need marketing that gives people more than cost/benefit of the individual product they are looking for. There is a reason Apple is Apple fyi. You might not like it, and you might think its dumb, but it works.
Wow, I've never seen so much effort been put into a BD family related fan vid!lol
AMD Ryzen Hype Ships
Original song : Conquest Of Paradise by Vagelis
Starcraft 2 is not something that requires higher FPS, you get to over 200FPS with a GTX 1050.
AMD is underplaying their relationship to Ryzen so that Ryzen can stand on its own, marketing-wise.
I would also like to say that the box, sitting on a shelf next Intel CPUs, will draw your attention through the use of negative space. And a little gloss can go a long way on top of that