See above my other comment on this.It's not comparable, because x86 is different. x86 has too much complex logic to translate complex instruction set into simple instruction set thus consume a lot more than any other ISA.
Not always true. Compare Apple's A9X with Intel's Core-M Skylake: both dual cores, but the latter is a bit smaller (there are some die shots made by some site).As you can see x86 core is quite big when compare to ARM.
Geekbench is a synthetic benchmark which means nothing.Discussion about frequency of an architecture is not difficult, but it would be quite unrealistic when comes to a specific product. Zen ES @ 32core start from 1.4Ghz according to Geekbench might be a hint, but there's nothing about its TDP.
I don't think so: take a look at my previous message on this topic.As I stated above, A9 has six decoders and no uop cache. This should more than compensate the x86 complexity.
Can you prove this relationship? To recap: do more pipeline states means lower FO4? How?Moreover A9 pipeline lenght is 16 stages versus 19 of Zen. So Zen has a lower FO4 delay
Well, previously you have written this:MIPS are MIPS and FLOPS are FLOPS. If you are talking about decoders, Zen has uop cache and decoders will be gated 50-90% of the time...
Moreover I underestimated all positive factors...
It's highly probable that it is custom, since in the past Apple acquired not only PA-Semi (which produced power-efficient PowerPC SoCs, mostly used for mission critical projects), but also Intrinsity, which was well known for its custom logic designs (see also the Titan project from AMCC, which largely used Intrinsity's technology / expertize).- Assumed that Apple can do a custom design and that A9X is not an ASIC, fact that is not sure...
ASICS has FO4>=30, custom designs have FO4<=25... At least 20% more clock at ISO power for Zen...
Even admitting A9X is a custom design,
Can you also prove that you (always) get a 20% clock increase on a chip, jumping from 16 to 19 stages?it has 16 stages versus 19, so in any case Zen can have clock 20% higher at the same Vcore.
I don't think so: take a look at my previous message on this topic.
Anyway, supposing that what you said is true: how did you measured such "compensation"? Have you made some calculations? Can you show them, so we can check how you got the numbers and verify them?
Can you prove this relationship? To recap: do more pipeline states means lower FO4? How?
It is not the delay of an inverter but the delay of a chain of three inverters with each inverter output being loaded by 4 inverters inputs.
To explain it simply an inverter drive four inverters, we take one of those 4 inverters and load its output with 4 inverters, so there s 3 stages, in the pic below there s two stage, so we add 4 gates that are driven by say the upper gate, the delay at the output of the third consecutive gate is the FO4 delay.
Well, previously you have written this:
"Zen has the uop cache, that reduces the consumption by the cache hit rate (I think between 50% and 80%)"And now you increased the second number by 10%. So, where did you got such numbers, and why you're changing them from time to time?
It's highly probable that it is custom, since in the past Apple acquired not only PA-Semi (which produced power-efficient PowerPC SoCs, mostly used for mission critical projects), but also Intrinsity, which was well known for its custom logic designs (see also the Titan project from AMCC, which largely used Intrinsity's technology / expertize).
Can you also prove that you (always) get a 20% clock increase on a chip, jumping from 16 to 19 stages?
Any thing to show bulldozer is 20 stages. I used to think it was that long, but now can only find comments from AMD saying its somewhere around 15/16. It could be 20ish for Floating Point.
It depends on the specific implementation.What is the hit rate of an uop cache? I posted 50%-80% because these were the estimations i found in other sites... Obviously will be 50% if it's small and 80-90% if it's big...
I already stated before (and also on the Italian's forum which we frequent) that ARM and x86 are too much different. Aside this, there are too much assumptions / if. For those reasons I don't think that such comparisons, and speculations too, don't make sense.I already done this calculation some posts ago, but briefly:
Let's assume decoder power being no more than 1/3 of total TDP (otherwise using x86 would be antieconomic)
With 80% hit rate, even if the x86 decoders draw double the power of ARM decoders, the penality on the TDP is 20%*1/3*2=13% on the total TDP.
I assumed that the 2 ARM core in the A9X does not draw all 5W because there is GPU, NB and SB. This can more than compensate the +13% given by the x86 penality
Regarding FO4: we know that Bulldozer has at most 20 stage pipelines: this is the maximum misperdiction penality... The articles on the internet ranges from 15 to this 20, also because there were not a paper that stated this precisely...
For Zen we know that it has 19 stage pipeline and A9X 16.
Most ARM design has FO4>=30, because are ASICs and reach anyway 2.5GHz in 4+4 big.little configurations (I recall Snapdragon 8x0, the top model at least), versus 1.85x2 of A9 and 2.26x2 on A9X
Anyway Zen pipelines seems to be similar to BD pipelines, that have a low FO4, estimated to be 17, giving the high clocks, up to 4.2GHz on 28nm BULK.
All these data let me think that Zen FO4 is similar to Bulldozer's and inferior to A9X's...
But even if Zen has same FO4 as A9X, the whole point of the calculations were to infer the feasibility of a 32c Zen core at 2GHz and 95W and given these data, i think that yes, you can...
OK, so there's no law/theorem behind it: just speculation.Mine were rough estimations. Indeed in my last post I used 80% to stay safer.
You are right that 16 to 19 stages does not imply +20% clock,
But you're comparing ARMs and x86s, which are too much different both in ISA and implementations: I don't subscribe it. It's already difficult to compare microimplementations of the same ISA...but as I said in the previous post, even if the FO4 is the same, the point was infer the feasibility of a 32c Zen 2Ghz 95W...
See above, but, well, I add another thing here: did you took a look at the ISA of ARMs and x86? x86 does more "useful work" on several instructions (and there are MANY of them), but it pays it in terms of power consumption (due to the more complex ALUs and FPUs).But since BD is 20 stages, we can deduce that Zen has similar Fo4 since are both x86 design of the same producer...
If the A9X has a low Fo4, why it does not reach at least low bulldozer clocks? Excavator on 28nm BULK draw 5W at 2.4GHz for two cores... A9X is on 14nmFF and draws 5W at 2.26GHz, and you all are saying that x86 is more complex of ARM and draw more power... So either Zen and BD has lower Fo4 than a9x or x86 tdp penality is not that much...
Nope. The "delay of an inverter" is closer to being correct. FO4 just describes the driving/loading condition of the inverter getting measured.
You need a realistic driver because input slope affects device delay and so the driver of the inverter should be sized 1/4th the size of the inverter under test.
You need a realistic load because an unloaded inverted (self loading only) makes it faster, so you put in 4 inverters of equal size as the load
And then usually for good measure, you want to do a FO4 loading on the load inverter due to deal with the miller cap issues on an unloaded inverter
It depends on the specific implementation.
Intel claimed about 80% hit ratio for its LSD (on the first implementation).
I already stated before (and also on the Italian's forum which we frequent) that ARM and x86 are too much different. Aside this, there are too much assumptions / if. For those reasons I don't think that such comparisons, and speculations too, don't make sense.
Anyway, I asked a different question before, regarding your previous statement. Should I assume that there's no prove for it?
OK, so there's no law/theorem behind it: just speculation.
But you're comparing ARMs and x86s, which are too much different both in ISA and implementations: I don't subscribe it. It's already difficult to compare microimplementations of the same ISA...
See above, but, well, I add another thing here: did you took a look at the ISA of ARMs and x86? x86 does more "useful work" on several instructions (and there are MANY of them), but it pays it in terms of power consumption (due to the more complex ALUs and FPUs).
But it can make sense IF the code can make use of such complexity. Which isn't always the case, albeit x86s shown very good and extremely competitive performances compared to the most "noble" RISC processors.
So, again, too much differences which makes not possible, IMO, to compare the two ISAs and their implementations.
One can use a set of benchmark, even real life applications, a power meter and decide which is the best.True. And now?
The problem is that the functional units are completely different.
I repeat again: have you took a look at the specific ISAs? How can you state that an ARM FPU is functionally similar to an x86 one, except that for a very high level point of view?
The problem is that the functional units are completely different.
Then you are measuring the consumption of the respective CPUs, but you cannot make assumptions about one based to the results of the other one, because they are completely different.
In fact, the difference is not only on the coding of the instructions, like you said, but how the respective FPUs get the instructions to execute, and do the real job. And, of course, if you disassembly the binaries, you'll find a very different set of instructions which is generated.
Doesnt matter to the extent that they mentioned the efficency of the new units in respect of the older ones..
Same power comsumption/cycle as Excavator, to summarize comsumption at same frequency but at twice the FP throughput for Zen is comparable.
At 3.5GHz an XV core consume 8W in Cinebench R15, so 8 Zen core should be within 65W not counting the uncore but this latter will also be much more efficient than in XV derived APUs, so the total figure should be about 80W.
It's not only a question of decoders. ISA matters ALSO in several other aspects, which nobody talk about unfortunately.Yes, but since the calculation done is the same, the useful switching are the same and if the low level units are the same, the power consumption of the FPU and ALU is the same. What changes is the consumption of the rest of the CPU. Even if the difference is +-50%, the most part of the power consumption is given by the FPU and ALU, at least 2/3. I was aiming at a rough estimation. More of an upper limit.
I know the x86 decoders are much power hungry. But probabily A9x does not have uop cache and probabily Zen's uop cache hit rate is about 80%, that means that the decoders draw 1/5 of the power... This can be sufficient to make their power consumption similar to 4-6 ARM decoder? How much power an x86 decoder draw? 1W?!?!?! I think not...
1) Excavator isn't an ARM processor.
2) You're using AMD's slides.
I prefer to wait for a power consumption analysis from tech sites like AnandTech, to see what really happens... on the real world.
Ah! At last... I didn't remember exact power consumption of an XV core...
BTW the same consumpiton is reasonable even if the FP is twice the size, since XV is on 28nm BULK and Zen on 14nmFF...