AMD Ryzen (Summit Ridge) Benchmarks Thread (use new thread)

[cdimauro]

Ok good night. I know you have not said I am stupid. But highlighting other errors without answering, is not pleasant, you should admit.

You know that I'm not used, and I don't need, to offend people: I'm fine politely talking of technical things. And that's what I did.

I have no time here, because I've to prepare to go to work, and then I go with the my family in vacation for this week-end, but I quickly give you some hints / opportunity to better check what I was talking about before.

1) No kernel mode. I was referring only to the regular user mode. And in Long Mode.
2) Segmentation is still active, but don't produce effects. Which is very different to say that it's disabled. Think ALSO about happens when an SMP core which runs 64 and 32 bit apps, one on each hardware thread; it's NOT an uncommon case, especially on Windows.
3) Even for a simple ADD operation, an x64 ALU has to take in consideration several things: different sizes (from 8 to 64 bit) with different operational modes (masking or clearing upper bits), always updating the flags (with its problem on the pipeline on an OoO uarch), the some flags are a bit dirty to handle (Auxiliary and Parity are still there). Last but not really least, operations like INC, which are very similar to ADD, in reality are different and require ad hoc / specific handling.
4) Even for a simple FADD, an x64 FPU has to take in consideration similar problems: different sizes (64, 128, 256, and the future 512 bit), masking/clearing of upper bits, using different registers set (64 bit = MMX). And of course there's the x87 legacy... with also 80-bit operations.
5) x64 has many many instructions, both on ALU and FPU side.
6) x64 has many different addressing modes, special encodings for them, and special behavior (e.g.: on 32 bit mode there's still DS and SS segment distinction... and you run also 32 bit code).

OK, I've to go now, but think about it.

Nice weekend.

 

[Justinbaileyman]

So do we know if Zen is going to beat the x99 platform or not? Say AMD's Top Zen model vs a Intel 6900K?? I just ask cause I have an amazing chance to jump on the x99 platform and get a 6900k now or should I just wait for Zen?If some one knows for sure please let me know.

 

[bjt2]

Yes, the fact that those Athlon are eventually second rate parts is a way to not underestimate anything, besides as you point it it s quite possible that the comparison in the slide is Bristol Ridge, wich would definitly make sure that estimations are a worst case figure.



The Vcore is slightly increased for the overclocking and power did increase by only 25% wich is the number for a process that would scale perfectly, this is of course not the case and it s likely that they are not within regular voltage margin, neverless their results point to the limitation being due to the BCLOCK method of overclocking.

From the curves AMD published Bristol Ridge power dissipation is significantly lower than Carrizo, possibly 6.5W/core at the same 3.5GHz and with a more efficient uncore, but for the time i prefer to be cautious and stick with the Athlon 845 as basis for estimations.

Very interesting... I ever thought the enhancement in Bristol Ridge were going to be negligible...
Anyway, assuming scaling exponent to be 1.7 (worst case) and 6.5W for 3.5 BR core, a 2GHz BR core should draw 6.5/(3.5/2)^1.7=2.51W, and so Zen, according to AMD. Pretty much in line with my estimations

You know that I'm not used, and I don't need, to offend people: I'm fine politely talking of technical things. And that's what I did.

I have no time here, because I've to prepare to go to work, and then I go with the my family in vacation for this week-end, but I quickly give you some hints / opportunity to better check what I was talking about before.

1) No kernel mode. I was referring only to the regular user mode. And in Long Mode.
2) Segmentation is still active, but don't produce effects. Which is very different to say that it's disabled. Think ALSO about happens when an SMP core which runs 64 and 32 bit apps, one on each hardware thread; it's NOT an uncommon case, especially on Windows.
3) Even for a simple ADD operation, an x64 ALU has to take in consideration several things: different sizes (from 8 to 64 bit) with different operational modes (masking or clearing upper bits), always updating the flags (with its problem on the pipeline on an OoO uarch), the some flags are a bit dirty to handle (Auxiliary and Parity are still there). Last but not really least, operations like INC, which are very similar to ADD, in reality are different and require ad hoc / specific handling.
4) Even for a simple FADD, an x64 FPU has to take in consideration similar problems: different sizes (64, 128, 256, and the future 512 bit), masking/clearing of upper bits, using different registers set (64 bit = MMX). And of course there's the x87 legacy... with also 80-bit operations.
5) x64 has many many instructions, both on ALU and FPU side.
6) x64 has many different addressing modes, special encodings for them, and special behavior (e.g.: on 32 bit mode there's still DS and SS segment distinction... and you run also 32 bit code).

OK, I've to go now, but think about it.

Nice weekend.

Nice weekend to you, too.

 

[The Stilt]

So do we know if Zen is going to beat the x99 platform or not? Say AMD's Top Zen model vs a Intel 6900K?? I just ask cause I have an amazing chance to jump on the x99 platform and get a 6900k now or should I just wait for Zen?If some one knows for sure please let me know.

There is no indication that Zeppelin will able to match, let alone better Broadwell-E. Based on just the figure released by AMD (40% higher IPC than Excavator), it should remain 10-20% behind in overall IPC and more in modern workloads which use 256-bit instructions. Even if Zeppelin would have a comparable IPC, it will be behind in the clocks. 6900K has an effective all core turbo frequency of 3.5GHz (non AVX2 workloads) and single core boost up to 3.7GHz. And obviously you can overclock it further, if you feel the need to do so. X99 platform combined with an 6900K also has quad channel memory for enhanced bandwidth and a higher number of PCI-E links than Zeppelin has.

 

[leoneazzurro]

There is no indication that Zeppelin will able to match, let alone better Broadwell-E. Based on just the figure released by AMD (40% higher IPC than Excavator), it should remain 10-20% behind in overall IPC and more in modern workloads which use 256-bit instructions.

This is quite likely to happen, however not all "modern workloads" will use 256 bit instructions and in FP128 bit code BW lead it is at least debatable.

Even if Zeppelin would have a comparable IPC, it will be behind in the clocks.

Source? Final clocks are not disclosed, I will be quite careful of declaring that for a given.

 

[krumme]

For a 180mm2 die at 95w tdp, on a cheaper platform, i hope The Stilt is correct, or this world is upside down. For some reason he just cant seem to frame it that way

 

[The Stilt]

Source? Final clocks are not disclosed, I will be quite careful of declaring that for a given.

Source for the personal experience and ability to think logically?

If we look when the final silicon revision for the previous releases came available, we are already beyond the 2016 / early 2017 release window if we expect that the current revision (ZP-A0) is not the final one.

Bulldozer - Week 23 of 2011 (June 6 - 12) assembly date of the first known launch stepping silicon (OR-B2), launched in 10.12.2011. Delta of >= 4 months+
Steamroller - Week 38 of 2013 (September 16 - 22) assembly date of the first known launch stepping silicon (KV-A1), launched in 1.14.2014. Delta of 4 months+
Excavator - Week 51 of 2014 (December 15 - 21) assembly date of the first known launch stepping silicon (CZ-A1), launched in 6.3.2015. Delta of 5 and half months+

The assembly dates are also newer than the actual manufacturing date of the silicon, since they are not immediately assembled after the silicon is finalized. Also the manufacturing for all of these parts was done in Germany, while the actual assembly occurred in Malaysia.

Also the software stack is usually the first indication for a new revision. There is no indication for anything else than just the ZP-A0 being in the works.

Sources for the first occurrences (assembly dates):

Bulldozer: http://www.ebay.com/itm/QTY-1x-AMD-...ZS262445TCG45-ES-CPU-G34-Tested-/141744454788
Steamroller: http://www.legitreviews.com/amd-kaveri-a8-7600-a10-7800-apu-review_147879
Excavator: http://www.ebay.com/itm/100-NEW-Original-AMD-ZM2111C1Y4382-BGA-ic-chip-with-balls/272224082433

 

[leoneazzurro]

He could be also right at the end, but at this moment it cannot be said for a given.

 

[leoneazzurro]

Source for the personal experience and ability to think logically?

If we look when the final silicon revision for the previous releases came available, we are already beyond the 2016 / early 2017 release window if we expect that the current revision (ZP-A0) is not the final one.

Bulldozer - Week 23 of 2011 (June 6 - 12) assembly date of the first known launch stepping silicon (OR-B2), launched in 10.12.2011. Delta of >= 4 months+
Steamroller - Week 38 of 2013 (September 16 - 22) assembly date of the first known launch stepping silicon (KV-A1), launched in 1.14.2014. Delta of 4 months+
Excavator - Week 51 of 2014 (December 15 - 21) assembly date of the first known launch stepping silicon (CZ-A1), launched in 6.3.2015. Delta of 5 and half months+

The assembly dates are also newer than the actual manufacturing date of the silicon, since they are not immediately assembled after the silicon is finalized. Also the manufacturing for all of these parts was done in Germany, while the actual assembly occurred in Malaysia.

Also the software stack is usually the first indication for a new revision. There is no indication for anything else than just the ZP-A0 being in the works.

Sources for the first occurences (assembly dates):

Bulldozer: http://www.ebay.com/itm/QTY-1x-AMD-...ZS262445TCG45-ES-CPU-G34-Tested-/141744454788
Steamroller: http://www.legitreviews.com/amd-kaveri-a8-7600-a10-7800-apu-review_147879
Excavator: http://www.ebay.com/itm/100-NEW-Original-AMD-ZM2111C1Y4382-BGA-ic-chip-with-balls/272224082433

So you have final silicon available and at final clocks and have performed all kinds of benchmarks on it. Probably not, OK, so no source and only your personal guess (let's call it "logical thinking", but a guess is what it is). Then at least write IMHO in it, otherwise don't whine when someone says you're trolling.

 

[krumme]

Ahh. Its all speculation. Lets have fun.
....but teasing is okey

 

[bjt2]

Bulldozer has integer pipeline length up to 20 (there is not an official paper, only speculations. Assume the worst, 20 stages) and on the 28nm BULK obtain 3.8GHz base and 4.2GHz turbo with under 10W /core.
Zen has integer pipeline of 19 stages (official paper linked by Dresdenboy), on the new 14nm FinFet, that promise up to 50% clock or up to -70% power consumption, AMD states that the Zen core has the same consumption per clock of a Excavator core, but with +40% IPC and many of you still think that Zen core can't clock over 3.2GHz? If we stick to AMD bold statements, at 3.2GHz a Zen core should draw perharps 5-6W and an 8 core Zen so should draw 50-60W... Forget the blender test, where Zen draw slightly less an underclocked BDW-E, because it's an ES and probabily had an high Vcore to avoid awful system freezes during a tough blender test...

I repeat myself: I would expect about the same clock of the 65W Bristol ridge APU, namely 3.8GHz base...

 

[The Stilt]

So you have final silicon available and at final clocks and have performed all kinds of benchmarks on it. Probably not, OK, so no source and only your personal guess (let's call it "logical thinking", but a guess is what it is). Then at least write IMHO in it, otherwise don't whine when someone says you're trolling.

So making statements based on currently known facts, which contradict your personal hopes and are not positive towards the company you are a fan of is considered trolling?

Could you please point out which of these statements are incorrect:

- The highest known frequency for any Zeppelin based part is currently 3.2GHz.
- AMD has currently demoed and shipped ZP-A0 revision parts to the partners.
- AMD demoed Zeppelin at 3.0GHz using Blender.
- The production of the final silicon revision generally starts at least four months prior to the release.
- Zeppelin is expected to launch in late 2016 (sampling) and Q1 2017 in volume according to AMD.
- Zeppelin uses 14nm LPP, which is a low power process. A type of process (low power) which in the past has never been used for high performance parts.

So based on these, you could try to answer these:

- If Zeppelin is capable for significantly higher clocks than just 3.2GHz, why is AMD sending so low clocked parts (including consumer SKUs) to partners for evaluation and why did they underclock the 6900K Broadwell-E for the Blender demo?
- Since newer than ZP-A0 silicon revision should exist at this point (based on the scheduled sampling / release), why are they still shipping old revision parts to the partners for evaluation?
- If the higher launch clocks are not the result from a new silicon revision, where do they originate?

 

[lolfail9001]

Bulldozer has integer pipeline length up to 20 (there is not an official paper, only speculations. Assume the worst, 20 stages) and on the 28nm BULK obtain 3.8GHz base and 4.2GHz turbo with under 10W /core.
Zen has integer pipeline of 19 stages (official paper linked by Dresdenboy), on the new 14nm FinFet, that promise up to 50% clock or up to -70% power consumption, AMD states that the Zen core has the same consumption per clock of a Excavator core, but with +40% IPC and many of you still think that Zen core can't clock over 3.2GHz? If we stick to AMD bold statements, at 3.2GHz a Zen core should draw perharps 5-6W and an 8 core Zen so should draw 50-60W... Forget the blender test, where Zen draw slightly less an underclocked BDW-E, because it's an ES and probabily had an high Vcore to avoid awful system freezes during a tough blender test...

I repeat myself: I would expect about the same clock of the 65W Bristol ridge APU, namely 3.8GHz base...

I'll repeat myself as well: pipeline is one of many things affecting clock potential as well. Look at a freaking Broadwell, for one. Minor architecture changes and suddenly it's potential fmax is a whole .5Ghz lower than Haswell's on conventional cooling and about 1Ghz with all cooling limits removed (as in, 3DMark stable-fmax). And frankly, LN2 fmax is as close as you can get to actual architecture/silicon-limited fmax.

As for AMD's bold statements, i still need to see power consumption numbers on Bristol Ridge, first.

 

[leoneazzurro]

Who Knows? Me and you surely not. But, between Bulldozer ES clocks and final launch clocks, i.e. there were 700 MHz of difference. Why do you consider only the hints that suit to you convinctions and ignore other facts that instead don't? Who is acting like a fanboy? I already stated my personal expectations on Zen and are these are not saying it will be an "Intel crusher", I expect it to have lesser IPC than BW, i.e. But I state quite clearly that these are OPINIONS, not FACTS. In you post you write down things as FACTS and this is not correct for whoever reads you.

 

[The Stilt]

Bulldozer has integer pipeline length up to 20 (there is not an official paper, only speculations. Assume the worst, 20 stages) and on the 28nm BULK obtain 3.8GHz base and 4.2GHz turbo with under 10W /core.
Zen has integer pipeline of 19 stages (official paper linked by Dresdenboy), on the new 14nm FinFet, that promise up to 50% clock or up to -70% power consumption, AMD states that the Zen core has the same consumption per clock of a Excavator core, but with +40% IPC and many of you still think that Zen core can't clock over 3.2GHz? If we stick to AMD bold statements, at 3.2GHz a Zen core should draw perharps 5-6W and an 8 core Zen so should draw 50-60W... Forget the blender test, where Zen draw slightly less an underclocked BDW-E, because it's an ES and probabily had an high Vcore to avoid awful system freezes during a tough blender test...

I repeat myself: I would expect about the same clock of the 65W Bristol ridge APU, namely 3.8GHz base...

Estimating the Fmax of a CPU simply based on "INT pipeline lenght" is pretty much the same thing as estimating the speed of a race horse based on it's teeth. On all AMD CPUs since K7 the first limiting factor has been the L2 cache. On 15h designs up to the magnitude where you could calculate the new Fmax based on the L2 latency in case it would be changed, while every other aspect remained the same. L1 was somewhat also an issue, however it scaled with much less effort than the L2. On Zeppelin the L2 latency is substatially lower than on 15h. Actually not substatially, but by a landslide. If FX-9590 had the same L2 latency as Zeppelin does, it would be clocked 2.8 / 3.0GHz instead of 4.7 / 5.0GHz.

 

[The Stilt]

But, between Bulldozer ES clocks and final launch clocks, i.e. there were 700 MHz of difference. Why do you consider only the hints that suit to you convinctions and ignore other facts that instead don't?

700MHz difference between the first prototype i.e A0 silicon, with 95W TDP (125W didn't exist prior B0) might have been the case. However in a similar time frame (less than 6 months to the release) ES parts operating at final clocks were well available, despite their even weren't the final / launch stepping.

ZD312051W8K44 - 4.1GHz - B0 stepping (125W)
ZD302051W8K44 - 4.0GHz - B0 stepping (125W)
ZD282051W8K44 - 3.8GHz - B0 stepping (125W)
ZD282046W6K43 - 3.6GHz - A1 Stepping (95W)

http://browser.primatelabs.com/geekbench3/6824628
https://www.techpowerup.com/forums/...mance-of-4ghz-bulldozer-es-vs-i7-990x.148244/

 

[cytg111]

Haswell ES was like 2.8 right? Still overclocked towards 5Ghz though, some over - and better than final silicon.
How do you hope to gain further information about Zen by beating the same dead horse that is the same minimalistic same data set as last week and the week before that? It makes no sense - at all.

 

[The Stilt]

Haswell ES was like 2.8 right? Still overclocked towards 5Ghz though, some over - and better than final silicon.
How do you hope to gain further information about Zen by beating the same dead horse that is the same minimalistic same data set as last week and the week before that? It makes no sense - at all.

Right, and did Intel set up a venue few months prior the launch to display it's performance at that 2.8GHz (1.1GHz lower than the launch frequencies were)?
I have exactly zero intention to beat the dead horse any further, I just corrected the inaccurate information posted by another user.

 

[leoneazzurro]

700MHz difference between the first prototype i.e A0 silicon, with 95W TDP (125W didn't exist prior B0) might have been the case. However in a similar time frame (less than 6 months to the release) ES parts operating at final clocks were well available, despite their even weren't the final / launch stepping.

ZD312051W8K44 - 4.1GHz - B0 stepping (125W)
ZD302051W8K44 - 4.0GHz - B0 stepping (125W)
ZD282051W8K44 - 3.8GHz - B0 stepping (125W)
ZD282046W6K43 - 3.6GHz - A1 Stepping (95W)

http://browser.primatelabs.com/geekbench3/6824628
https://www.techpowerup.com/forums/...mance-of-4ghz-bulldozer-es-vs-i7-990x.148244/

First chip was overclocked (and nobody so far did the same with a Zen die, AFAIK), second one says 3,2 GHz (and upload date 2nd of june, 2016, lol) , and Bulldozer launched at 3.6GHz base with a 3.9 GHz turbo. First BD sample appeared at 2,8 GHz. Also, AMD did non publicy disclose actual benchmarks at that time. But anyway, all of this is only speculation and of course you are entitled of your opinion. I hope only you will cease to treat it like a fact set in stone.

 

[The Stilt]

First chip was overclocked (and nobody so far did the same with a Zen die, AFAIK), second one says 3,2 GHz (and upload date 2nd of june, 2016, lol) , and Bulldozer launched at 3.6GHz base with a 3.9 GHz turbo. First BD sample appeared at 2,8 GHz. Also, AMD did non publicy disclose actual benchmarks at that time. But anyway, all of this is only speculation and of course you are entitled of your opinion. I hope only you will cease to treat it like a fact set in stone.

I provided the link just for reference, the clocks I mentioned are the maximum defaults for those SKUs.
FX-8150 launched at 3.6GHz base and 4.2GHz maximum turbo.

 

[bjt2]

Estimating the Fmax of a CPU simply based on "INT pipeline lenght" is pretty much the same thing as estimating the speed of a race horse based on it's teeth. On all AMD CPUs since K7 the first limiting factor has been the L2 cache. On 15h designs up to the magnitude where you could calculate the new Fmax based on the L2 latency in case it would be changed, while every other aspect remained the same. L1 was somewhat also an issue, however it scaled with much less effort than the L2. On Zeppelin the L2 latency is substatially lower than on 15h. Actually not substatially, but by a landslide. If FX-9590 had the same L2 latency as Zeppelin does, it would be clocked 2.8 / 3.0GHz instead of 4.7 / 5.0GHz.

Zen L2 is inclusive and does not have 4 buses to 2 L1 caches. Also is 1/4 of the size.
Also i am confident that this time they have balanced the FO4 of every stage. As you may know, it is not efficient have pipeline stages with very much different delay...

 

[Justinbaileyman]

Ok so there is little real info on the ZEN but from what we know do we know what the memory standard is going to be beyond the fact of it using DDR4?

 

[Abwx]

So making statements based on currently known facts, which contradict your personal hopes and are not positive towards the company you are a fan of is considered trolling?

But you said earlier that we have no element to make a comparison with BDW yet you are insisting that it wont perform as well in all your posts, so who is basing his opinion on brand preference if not aversion..?..

At least we are using an actual number even if it s provided by AMD while all your "logic" is more or less based on fud, prove is your constant reference to BD, not even to its late XV iteration, why not the K5 while you re at it..?.

- If Zeppelin is capable for significantly higher clocks than just 3.2GHz, why is AMD sending so low clocked parts (including consumer SKUs) to partners for evaluation and why did they underclock the 6900K Broadwell-E for the Blender demo?

When you send ESs to OEMs you make sure that they are 100% stable, so this mean cut down frequencies and overvolting on top, indeed someone pointed that their competitor did send Haswell ESs that were clocked as low, and not even sure that they got a 3.2 turbo...

They fixed the frequency at 3GHz to make a clock/clock comparison and display that they have better IPC in this software, that s what the rep said during the demo :

https://www.youtube.com/watch?v=oQS8s7TOXsE

And as pointed ad nauseam they stated that Zen consumed "a little less" than BDW during this demo, and personaly i think that it s rather significantly less because they surely used the stock voltages and reviews proved that BDW-E is highly undervolted and is out of specs in respect of the minimal voltage margins used in the industry, i guess that like the X99 plateform MBs will "unexpectedly overvolt" those CPUs..

 

[The Stilt]

But you said earlier that we have no element to make a comparison with BDW yet you are insisting that it wont perform as well in all your posts, so who is basing his opinion on brand preference if not aversion..?..
At least we are using an actual number even if it s provided by AMD while all your "logic" is more or less based on fud, prove is your constant reference to BD, not even to its late XV iteration, why not the K5 while you re at it..?.

Can you elaborate?
There is only a single piece of information I base the estimation for Zen's IPC on. And that information came directly from the horse's mouth (40% over Excavator). If Broadwell & Skylake have > 60% higher IPC than Excavator in certain FP workloads, will Zen's 40% higher IPC over Excavator bring the IPC to par with Broadwell and Skylake? i.e is 40% <> 60%?

Also, could you define "fud" with your own words? I'm really not familiar with the term and you seem to blame me for spreading "fud" all the time.
Until now I've thought that it refers to an unpleasant fact, unsuitable for your agenda.

So if spreading "fud" equals spreading lies, please point out any lie I've ever posted. Maybe I should mention that something you are personally not agreeing on, doesn't qualify as a lie.

 

[Justinbaileyman]

Never mind then I guess it wasn't meant to be and I'll have to wait on Zen now. Someone snagged that 6900k off of ebay before I could make up my mind to pull the trigger. Not only that but newegg just raised the price back up on the motherboard I was about to purchase 2 wammy's in one day is a sign from up above to hold my horses. Guess I will start looking at DDR4 then to get me ready for Bristol Ridge or Zen..