There are two sides: a scheduler having more things to consider needs more time, but also more power. Zen's FP scheduler is of medium complexity given its 4 issue ports.So is the bottom line here that running a unified scheduler at high frequencies is tougher to implement than separate Int/FP schedulers at high frequency?
There are two sides: a scheduler having more things to consider needs more time, but also more power. Zen's FP scheduler is of medium complexity given its 4 issue ports.
Somewhat simpler schedulers (like a group of single INT schedulers) may occasionally lose a cycle, which weighs more, the more pressure there is on the schedulers.
The number of combinations is greatly lower than O(n!). And to be more specific, the problem of dispatching one uop to one (and only one) of the free ports (from the list of allowed ones for this specific uop) is fairly simple and fast to solve; even optimized taking some design decisions.The possible combinations, and the required logic, grows with the factiorial (n!), so it's useful to split into domain. Power 8 and 9 have more domains: int, branch, memory and FP (and maybe i forgot something).
Disassembling some code you can see that there are some, but the problem is determining how many of them are executed at runtime. Here, you need a (good) profiler.But yes this comes at one price: longer latencies on intructions that move data between domains... I don0t think that they are more than a few percent of the executed instructions...
That's only an implementation detail, but anyway Zen's ALUs are not symmetrical (they are specialized for some specific operations to be executed), so you need to know which of the (free) schedulers/ALUs need to be selected.This is a simple scheduling. Actually can also be a single bit in the uop, that can be set by the decoders...
@Abwx: the strange thing is that, according to the slides, Zen's uop cache can dispatch a maximum of 6 uops to schedulers...
Finally, the dispatch can apply six instructions per cycle, at a maximum rate of 6/cycle to the INT scheduler or 4/cycle to the FP scheduler. We confirmed with AMD that the dispatch unit can simultaneously dispatch to both INT and FP inside the same cycle
http://www.hardware.fr/news/14758/amd-detaille-architecture-zen.htmlEn pratique 10 micro ops peuvent être envoyées (6 vers la partie "Integer" de la puce, 4 vers la partie "Floating Point")
6 uops/cycle can be dispatched to the INT schedulers unit and 4 uops/cycle to the FPU scheduler, simultaneously.
From this link:6 uops/cycle can be dispatched to the INT schedulers unit and 4 uops/cycle to the FPU scheduler, simultaneously.
http://www.anandtech.com/show/10591/amd-zen-microarchiture-part-2-extracting-instructionlevel-parallelism/3
From this link:
This is also pointed by hardware.fr journalist :
http://www.hardware.fr/news/14758/amd-detaille-architecture-zen.html
Selective application of facts.You said that unless Intel puts eDRAM on their CPUs, you will wait for Zen. I am telling you that Zen CPUs/APUs do not have eDRAM, something that is pretty common knowledge at this point. It would seem to me that you are applying what is called a "double standard" -- in other words, Intel needs to have eDRAM to be interesting to you, but AMD can get a free pass.
That, to me, suggests a potential bias towards AMD products.
Read Peter Bright's article and post a rebuttal if you can think of one.6700K for $340 is a pretty good deal for the kind of performance you can get -- meaningfully faster than prior generation Intel CPUs and leagues ahead of anything AMD currently offers. Why be disappointed?
EDRAM is separately clocked. The added cost and complexity of Intel devoting half of the CPU chip to iGPU is a lot more questionable.A mainstream socketed desktop CPU with eDRAM and a big iGPU just isn't an attractive value proposition for most people, especially since it adds cost and could potentially negatively impact overclocking headroom.
Are you suggesting that AMD cannot offer a price-competitive part but Intel and Nvidia will?Even when AMD fielded competitive products, pricing on high-end GPUs has been "high." Fortunately, NVIDIA offers products at just about every relevant price point, so buy to your budget.
1) Ships with an EDRAM controller but has no EDRAM, causing it to lose to the older Broadwell C, or be matched by it — despite a clock deficit.What drawbacks are there in Skylake?
Does the Skylake 4+2 die really have the EDRAM controller? It's pretty big, you would think it would be removed since they aren't using it.
Anandtech 9-1-2015 said:For Skylake, eDRAM enabled processors will be configured differently to previous versions in order to make the effect of the eDRAM more seamless for software.
In Skylake, the eDRAM arrangement changes:
Rather than acting as a pseudo-L4 cache, the eDRAM becomes a DRAM buffer and automatically transparent to any software (CPU or IGP) that requires DRAM access. As a result, other hardware that communicates through the system agent (such as PCIe devices or data from the chipset) and requires information in DRAM does not need to navigate through the L3 cache on the processor. Technically graphics workloads still need to circle around the system agent, perhaps drawing a little more power, but GPU drivers need not worry about the size of the eDRAM when it becomes buffer-esque and is accessed before the memory controller is adjusted into a higher power read request. The underlying message is that the eDRAM is now observed by all DRAM accesses, allowing it to be fully coherent and no need for it to be flushed to maintain that coherence. Also, for display engine tasks, it can bypass the L3 when required in a standard DRAM access scenario. While the purpose of the eDRAM is to be as seamless as possible, Intel is allowing some level on control at the driver level allowing textures larger than the L3 to reside only in eDRAM in order to prevent overwriting the data contained in the L3 and having to recache it for other workloads.
A number of media have already been requesting an announcement regarding a discrete processor with an eDRAM implementation, similar to Broadwell. I even enjoyed conversations at IDF where it was suggested that Intel could produce an i7 at 4.0 GHz with 128MB eDRAM, either with or without overclocking, and charge a nice $30-$50 premium for it. ... For users who actively want an LGA1151 4+4e configuration, make sure your Intel representative knows it, because customer requests travel up the chain.
Everything I read about it said it shipped with the controller but not with EDRAM installed.WCCFtech said:Intel Skylake Gen9 Graphics Features:
Gen9 Memory Hierarchy Refinements:
In Gen9 EDRAM now acts as a memory-side cache between LLC and DRAM. Also, the EDRAM memory controller has moved into the system agent, adjacent to the display controller, to support power efficient and low latency display refresh.
More surprisingly, the 6700K die also houses an optional eDRAM controller that can feature 64 MB to 128 MB of eDRAM (L4) cache with frequencies of up to 1.6 GHz to increase bandwidth, reduce latency and improve performance on faster iGPUs.
Anandtech 9-15-2016 said:Some could argue that going for a Crystal Well based processor, with added embedded DRAM (eDRAM), might be more helpful in certain memory limited situations. This is true ... like WinZip compression, this shows in the results. Something like the ... i7-5775C have 128MB of eDRAM that acts like a victim cache and can optimise most gains (up to 128MB) as long as the software is recalling frequently used memory due to the victim cache nature. The latest iteration of eDRAM processors such as the i7-6770HQ, where the eDRAM acts as a true DRAM buffer...
This is not what the statement says. It says it can dispatch up to 6 to INT, up to 4 to FP, and to both on the same cycle, but there is no statement whatsoever on it being able to dispatch the full throughput to both on the same cycle. I would be extremely surprised if it could -- this would be a costly feature to support, and would not really help much in real-world code.
En pratique 10 micro ops peuvent être envoyées (6 vers la partie "Integer" de la puce, 4 vers la partie "Floating Point")
Yes, but if in such dispatcher only 6 uops are entered, how can it dispatch 10?That s not what the hardware.fr journalist is saying :
Litteraly translated :
In practice 10 micro ops may be sent (6 toward the "Integer" of the chip, 4 to the "Floating Point"), two more than Haswell ...
In the slide i posted there s two output paths from the dispatcher, one go to the Integer schedulerq and the other to the FP scheduler, AMD s Mike Clark explicitely stated that the two parts of the CPU works as two independants processors according to Hardware.fr article.
https://translate.googleusercontent...n.html&usg=ALkJrhhdx7hNYCyhmV97bOgsUF_cXRWo_w
Remember that it was only implemented as a victim cache in Broadwell C. Skylake, by contrast, was developed so it can be used as a DRAM buffer.eDRAM is overrated.
The 4790K isn't clocked at the level of Broadwell C nor did it have the same low TDP.I mean, Skylake in initial reviews was losing to 4790k in some benches, so now what?
Yes, but if in such dispatcher only 6 uops are entered, how can it dispatch 10?
From this link:
"Finally, the dispatch can apply six instructions per cycle, at a maximum rate of 6/cycle to the INT scheduler or 4/cycle to the FP scheduler."
From this link:
"6 ops dispatched" (from the Micro-op Queue to the decoders)So, the decoders can get a maximum of 6 uops per cycle from the Micro-op Queue, and those 6 can be split between the INT and/or FP schedulers, with up to 6 and up to 4 respectively.
This doesn't mean that the maximum of dispatched uops is 6 + 4 = 10: it's still 6, which is the limited imposed by the Micro-op Queue.
Finally, the dispatch can apply six instructions per cycle, at a maximum rate of 6/cycle to the INT scheduler or 4/cycle to the FP scheduler. We confirmed with AMD that the dispatch unit can simultaneously dispatch to both INT and FP inside the same cycle, which can maximize throughput (the alternative would be to alternate each cycle, which reduces efficiency).
So if it can dispatch to the two schedulers in the same cycle it is clear that it can dispatch as much as 10 uops during a same cycle, indeed you didnt quote the whole text since it contradict your own point, or rather the lack of, i guess that it s a school case of cutting a text so it means the contrary of what it s supposed to mean on the first place...
I am not a computer engineer, but I believe the correct translation of that statement is that the micro-op cache can dispatch up to 6 ops total per cycle, where the INT side can accept up to 6 ops and the FP side can accept up to 4 ops. Therefore, any combination of ops to each side, up to 6 total, can be made, e.g. 6 ops to INT and 0 to FP, or 2 to INT and 4 to FP, or 3 to INT and 3 to FP, or 0 to INT and 4 to FP, etc.
Therefore, any combination of ops to each side, up to 6 total, can be made, e.g. 6 ops to INT and 0 to FP, or 2 to INT and 4 to FP, or 3 to INT and 3 to FP, or 0 to INT and 4 to FP, etc.
I'm sure it would be great to have that micro-op queue be able to dispatch to each and every port (all 6 INT and all 4 FP) but I bet the likelihood that there will be an op for each execution unit in a given cycle is rather slim, which explains why the total dispatch rate is reduced to 6 ops/cycle. 6 is probably the optimal number per AMD's internal testing; any less and you start starving the execution units for the design workload (factoring in SMT to help feed the execution units), and more than 6 is probably an inefficient use of die space or power given that most programs probably don't require processing over 4 ALUs, 2 AGUs, 2 FP MULs, and 2 FP ADDs in a given cycle.If more than 6 uops are available in the uop queue, say 6 INT uops and 4 FP uops, it wouldnt make sense that only 6 could be dispatched as to do so only a few more registers would be needed, the paths are clearly separated and the uops are already tagged, so it would cost nothing complexity wise to dispatch 10 uops with said repartition.
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The 6 vs. 10 uop dispatch likely causes a performance delta less than typical error margins. You might win less processing time on a Zen in a month than you spend here reading researching, and writing answers related to this topic.
Also worth considering:
Being able to simultaneously dispatch to INT and FP doesn't necessarily mean up to 10 uops, because a typical case of FP x86 instructions with mem ops would also both issue to FP and INT. The latter means to the AGUs and maybe one of the ALUs responsible for SSE/AVX MOVs according to the patch.
Nevertheless, if the Micro-op Cache can deliver a maximum of 6 uops/cycle, this is clearly the upper bound for both INT and FP decoders.
it was a lapsus. Decoders -> dispatchersIt is stated that de decoders are four... It would not make sense, power wise, to add more decoders... Even if the hit rate in the uop cache is only 50%, the decoders can produce at least the same uops than the 2x4 decoders in excavator, for 2 threads... But this time the two threads have 4 alu, 2 agu+l/s and 4 fp pipelines, instead of the 4 alu, 4 agu+l/s and 4 fp pipelines...
If the uop cache is big enough, the hit rate can be as high as 80%... And so the 4 decoders maybe are even too much...
I think that the first improvement that they will make in Zen+ is to beef up the uopache, without loose frequency... I bet that they are doing a lot of simulations on this topic...