Interesting thought. But I think using a L3$ chip vs. a max. L2$ chip is fair, because of this 40% including the L3$. It should mitigate the effect of the smaller L2$.
Interesting thought. But I think using a L3$ chip vs. a max. L2$ chip is fair, because of this 40% including the L3$. It should mitigate the effect of the smaller L2$.I would suggest you use the Core i3 6100 instead, A12-9800 is an APU with L2 cache only at 65W TDP when BD-E 6950K is a L3 25MB at 140W TDP SKU.
Yes,usually it does,but ever since AMD won the lawsuit against them about what constitutes a core they pretty much have the card blanche to use any technical term in any way they like,I mean they are selling 12 core laptops now because of this...there is no trust anymore.IPC usually means measured intructions per clock over several cycles (e.g. 1M, or all cycles of an application run), not "issue width", which is kind of a peak value, as the decoders and µOp$ simply can't provide enough instructions per cycle.
Intel has specialized execution units that reduce the cycles that instructions need until they are done.Sometimes even smart people might run into kind of a dead end, thought-wise. Then it might help to take them out of their seat, shake them a bit, and put them back in place. Or alternatively, one might kindly ask them to step back and check their POV.
I'd expected some ratio: % of max possible, not of all.
Here is an explanation:
http://www.eetimes.com/document.asp?doc_id=1276117
Zen likely has roughly similar values.
Intel has specialized execution units that reduce the cycles that instructions need until they are done.
OK, there are so many fallacies and mistakes in here, that I won't continue this discussion.Yes,usually it does,but ever since AMD won the lawsuit against them about what constitutes a core they pretty much have the card blanche to use any technical term in any way they like,I mean they are selling 12 core laptops now because of this...there is no trust anymore.
Intel has specialized execution units that reduce the cycles that instructions need until they are done.
If blender can actually use all available instructions,10 for ZEN and 8 for broadwell,then ZEN had to be 20% faster to match the "measured intructions per clock over several cycles" you mentioned,it doesn't so it is slower.
Even in the scenario when the software can use all instructions...as you said, most software doesn't.
8% is not bad. Depending on the code changes and code path selection for Zen, there might be zero to a small change.Cycles has recently received quite a few SIMD optimizations, so it might be worth to check the differences between the old and the current builds. The developers reported 8% reduction in rendering time from a single commit improving AVX2 (IIRC) alone, in the "BMW" scene.
The developers reported 8% reduction in rendering time from a single commit improving AVX2 (IIRC) alone, in the "BMW" scene.
8% is not bad. Depending on the code changes and code path selection for Zen, there might be zero to a small change.
I don't have a Core i3 6100 available to me at the moment, sorry. Anyway, the i3 6100 is Skylake based and the L3$ is actually a lot faster on SKL than it is on BDW-E (2.8GHz only). GB4 likes L3$ speed more than it likes L3$ size, AFAICT.
Interesting thought. But I think using a L3$ chip vs. a max. L2$ chip is fair, because of this 40% including the L3$. It should mitigate the effect of the smaller L2$.
That's really strange, since looking at Blender's code it shouldn't make use of 256-bit vectors.The devs were not lying.
In Blender 2.78 AVX2 is indeed beneficial. I measured > 11.8% average performance improvement from enabling AVX2. The SMT yield seems to be coming down to sane levels too (> 59% in 2.77, > 35% in 2.78).
Binaries compiled with MSVC 2015.
Tested with the "BMW Rev. 4" scene, 1920x1080 resolution, 40x40 tile size (96 X, 54 Y), on Haswell-EP HCC (18C/36T).
Non-AVX2: 270.52s
AVX2: 241.89s
Blender 2.78 - MSVC 2015, AVX2 / Non-AVX2) (111MB).
Pass: "blender" (without the quotes).
For Intel it doesn't matter, even with 65W such a Singlethread test with Geekbench is no issue, it performs with max clock. As for AMD it just shows that their Turbo implementation is very weak, I really doubt their CPU needs more than 45W when only one core is fully loaded, especially in Geekbench.
That's really strange, since looking at Blender's code it shouldn't make use of 256-bit vectors.
Can you try to force the usage of 128-bit sized vector registers with AVX code, if possible?
Maybe I didn't understand your point, but this is a simplistic form of my view here:
For ST (@iso freq):
T'put = #inst./cycle
Speed= #inst./cycle
And who said, that in real ST code XV constantly maxes out an IPC of 7.0 (2ALU+2AGU+3FP)? Why would a SW need to reach 10 ops/clock if in reality the value is more like 1.0 to 3.0, sometimes higher
I was speaking for Intel... no, that's not true. I just roughly remembered what is sometimes seen in papers.I ran an analysis on Thuban a while back using Code Analyst. Typical was 0.7-1.3 IPC. Max was 2.2 IPC by Prime95
That's why it can pull so much more power than typical appsI was speaking for Intel... no, that's not true. I just roughly remembered what is sometimes seen in papers.
But based on your measurements, Intel's current cores with improved mem access handling over Thuban, etc., should land somewhere in the range I gave.
I'm not surprised about Prime95. <storymode>While discussing with George Woltman and others about K8 optimizations, I learned a lot of interesting things about the SSE2 (P4) optimizations. Prime95's split radix FFTs were 3 times faster than the next fastest lib (FFTW, IIRC). George did not only schedule SSE2 instructions to perfection (and FFT radixes of course), but also did nice tricks with TLBs, etc.
Yep, close to a power virus, but doing useful calculations.That's why it can pull so much more power than typical apps