AMD Ryzen (Summit Ridge) Benchmarks Thread (use new thread)

[lolfail9001]

That s the other way around, check at Hardware.fr, the HW samples they received from Intel were within the official TDP, the retails versions they used a few months later showed that under Prime 95 Intel CPUs were exceding their TDP on a continous basis, while they measured nothing of the sort with any AMD CPU, so much for the ever going urban legends invariably spread by the same suspects..

I'll just ask for source because looking at their reviews i sure cannot find too many of Prime95 measurements and those that are done at ATX12V do have undershoot of TDP in Prime95.

 

[mikk]

That s the other way around, check at Hardware.fr, the HW samples they received from Intel were within the official TDP, the retails versions they used a few months later showed that under Prime 95 Intel CPUs were exceding their TDP on a continous basis, while they measured nothing of the sort with any AMD CPU, so much for the ever going urban legends invariably spread by the same suspects..

We are not talking about Prime95, we are talking about real world. Because at the moment AMD does not support AVX2 and it is doubtful that they can match AVX2 from Intel with Zen. So comparing Cinebench R15 results and then using power numbers from Prime95 won't give you the real picture about the power efficiency. Look at real world with the same instruction set for both.

 

[Arachnotronic]

Have you checked the rest of the thread, and posts of this person? He claims that 8 core/16 thread CPU with 5960X performance can cost roughly 300$.

If this turn out to be true...

LOL, ain't nobody selling 5960X performance for $300.

Price follows performance. Period.

 

[swilli89]

LOL, ain't nobody selling 5960X performance for $300.

Price follows performance. Period.

Yep, if AMD somehow brought out a product that replicated 5960X performance it will be $500+

 

[superstition]

Yep, if AMD somehow brought out a product that replicated 5960X performance it will be $500+

The only way AMD won't compete on price is if it bests Intel's performance which won't happen. So, AMD will compete on price no matter how many times Lisa Su said AMD wants to get a better profit margin on its chips.

Getting a better margin isn't the same thing as losing money on them.

Zen's design looks to be made to compete on price in the first place.

 

[KTE]

I will guarantee you that's an Intel shil/fanboy post.

Most of those details were in the rumors before Bulldozer. With a little 'spice'.

Price certainly does follow performance in the corporate world.

Sent from HTC 10
(Opinions are own)

 

[itsmydamnation]

The only way AMD won't compete on price is if it bests Intel's performance which won't happen. So, AMD will compete on price no matter how many times Lisa Su said AMD wants to get a better profit margin on its chips.

Getting a better margin isn't the same thing as losing money on them.

Zen's design looks to be made to compete on price in the first place.

no it doesn't. Care to show how?

 

[deasd]

The only way AMD won't compete on price is if it bests Intel's performance which won't happen. So, AMD will compete on price no matter how many times Lisa Su said AMD wants to get a better profit margin on its chips.

Getting a better margin isn't the same thing as losing money on them.

Zen's design looks to be made to compete on price in the first place.

This. BTW I agree with a post which I forget when it's being posted in this thread with similar point of view.

Looks like Zen has worse IPC and clocks than Kabylake or even Skylake, this is why Zen has to be compete on price, but still it's a way better than the situation they have now.

Zen STILL have to compete with newest product of intel with MOAR cores, thus lower price with same core count. I can infer that 8C16T Zen would be a bit expensive than i7-7700k, but I won't be surprise it would be cheaper than everyone here expected, not to mention Zen is likely to have cheaper mobo than intel. I guess around 400USD$ when it is launched.

 

[AtenRa]

The only way AMD won't compete on price is if it bests Intel's performance which won't happen. So, AMD will compete on price no matter how many times Lisa Su said AMD wants to get a better profit margin on its chips.

Getting a better margin isn't the same thing as losing money on them.

Zen's design looks to be made to compete on price in the first place.

They can compete on price and have higher margins than today, they dont need to directly compete in performance vs Intel Skylake/Kabylake.

Currently AMDs higher priced SKU is the FX 9590 priced at $229. This is a 300mm2 32nm product that NOBODY buys today.

Selling a 180-200mm2 ZEN SKU for $400-500 and increase sales volume over current FX 9xxx series of SKUs will dramatically increase margins.

What ZEN will do is to increase the Price segments of AMDs SKUs from the sub $300 of today, to higher than $400-500. They dont need to directly compete Core to Core/clock to clock against Intel, they only have to give an acceptably performance to price ratio that will allow them to increase their margins, sales volumes and thus profits.

Example, price a 6C 12T ZEN for the same price as 4C 8T Kabylake. That means they will sell a 180-200mm2 ZEN die for $300-350, or sell a 4C 8T at $220-250 vs Intel 4C 4T Core i5.
Selling a 4C 8T ZEN SKU at $230-250 at 2x-3x or more the volume of current FX 8xxx quarter sales, will be doable and will dramatically increase their Margins and profits.

 

[bjt2]

Interesting consideration on semi's thread...
I will expand it, adding some other considerations.

We know that interposer size limit for Fiji GPUs was around 1000mm2.
We know that AMD will propose quad die 32 cores Naples CPUs.
This put an upper limit on Zen die size of about 250mm2... Or else AMD must switch to another package technology.

Another consideration for upper limit is the TDP.
We currently know only the existence of 95W SKUs.
The dissipation limit is 0.5W/mm2.
So Zen die should be at least 190mm2.
A 140W model will require to break this rule or have 280mm2 dices...

These are not rules set in stone, but a good indicator for die size...

 

[lolfail9001]

This put an upper limit on Zen die size of about 250mm2... Or else AMD must switch to another package technology.

MCM package and HBM do not have to use same interposer.

The dissipation limit is 0.5W/mm2.

What is that limit in the first place?

 

[bjt2]

MCM package and HBM do not have to use same interposer.

Indeed I said that they should use another packaging technology, MCM for instance. But this poses limits on pin speed and power drain. The advantage of an interposer is to have many connections with lower power... HyperTransport doesn't scale well beyond 6.4GT/s... Probabily this is true also with interposer... But you can stuff 1024 bit buses, instead of 16-128 bit buses... And with a lower power consumption per pin... I think that AMD does not want to lose this train...

What is that limit in the first place?

I have heard many times this as an upper soft limit for power dissipation in silicon chips... As I said it's not set in stone, but intuitively there should be an upper limit to power dissipation, because the thermal conducibility is not infinity...

 

[The Stilt]

We know that interposer size limit for Fiji GPUs was around 1000mm2.
We know that AMD will propose quad die 32 cores Naples CPUs.
This put an upper limit on Zen die size of about 250mm2... Or else AMD must switch to another package technology.

Why do you even expect that there is an interposer on Zeppelin based MCM parts?

 

[DrMrLordX]

Does that 1.3 to 1.5 volt operating range jump off the page to anyone else?

Not really. If the leakage characteristics are highly-favorable, the result is high voltage tolerance within a given TDP range. How it scales with voltage is another matter altogether . . .

 

[bjt2]

Why do you even expect that there is an interposer on Zeppelin based MCM parts?

Because i hope so for bandwidth and power reasons... I always espect for a technical advancement...

And since there will be HPC APU with HMB2, and so with the interposer, I feel wrong to use different technologies for similar tasks: you must setup a production line for Zen HPC APU with interposer, and then another production line for MCM Zen CPUs? I think this is silly...

The interposer gives you a technical advantage over INTEL, that is stuck with monolitic dices (if it wants high performance with low power) that are enormous and dishomogeneous, forcing them to harvest and disable weak cores on bigger dices to have a decent clock...

With tiny 8 core dices and interposer, you can have near monolithic performance and power drain, but with the advantage of coupling similar cores together...

With MCM you must go off chip, with all the power and count constraints, and if you want not to be forced to allocate pins on the socket, you must use a "miniboard" on which put the dices...

 

[bjt2]

Not really. If the leakage characteristics are highly-favorable, the result is high voltage tolerance within a given TDP range. How it scales with voltage is another matter altogether . . .

Since with BULK the gate wraps the channel on only one side, and finfet on three sides, the transconductance should be far superior. And the Vth should be inferior due to the smaller process. The only unknown is on the parasitic capacitances. I don't know if they are less than a 28nm bulk... But I think that the absolute FO4 delay should be inferior, at same Vcore...

 

[Abwx]

Since with BULK the gate wraps the channel on only one side, and finfet on three sides, the transconductance should be far superior. And the Vth should be inferior due to the smaller process. The only unknown is on the parasitic capacitances. I don't know if they are less than a 28nm bulk.....

Vth doesnt scale down with process because laws of physics do not scale, as such VTHs have been fairly the same for several nodes.

Finfets have bigger input capacitance than planar but this is compensated by the smaller processes as well as higher transconductance wich allow lower voltages at a same speed at a given capacitive load.

 

[bjt2]

Vth doesnt scale down with process because laws of physics do not scale, as such VTHs have been fairly the same for several nodes.

Finfets have bigger input capacitance than planar but this is compensated by the smaller processes as well as higher transconductance wich allow lower voltages at a same speed at a given capacitive load.

Ok, so the lower voltage needed, e.g, for Polaris, at same clock is due only to transconductance/capacitance balance? Vth between 28nm and 14nm was not lowered even a bit?
I didn't know this... I ever thought that also Vth would drop...
So RVT, HVT and LVT transistors have the same Vth on both processes?
And the sLVT transistors, unique to the 14nm FF process? Is their Vth not lower than 28nm LVTs?

 

[Abwx]

Ok, so the lower voltage needed, e.g, for Polaris, at same clock is due only to transconductance/capacitance balance? Vth between 28nm and 14nm was not lowered even a bit?
I didn't know this... I ever thought that also Vth would drop...
So RVT, HVT and LVT transistors have the same Vth on both processes?
And the sLVT transistors, unique to the 14nm FF process? Is their Vth not lower than 28nm LVTs?

Yes, lower voltage is allowed by higher transconductance because speed is the ratio gm/C with gm being the transconductance and C the capacitance.

Tranconductance of a transistor is the slope of Vin/Iout, in plain words the resulting output current in function of an input voltage, higher transconductance mean that the device has higher output current for a given input voltage, so it will charge the driven capacitance faster due to this higher delivered current.

If transconductance is not high enough then the transistor conduction can be increased only by mean of higher supply voltage wich will allow higher drive voltages, but will also increase the energy stored in the switching capacitances and hence losses.

Because fets transconductances are a square law, meaning that the output current increase as the square of the input voltage, doubling the conduction and hence speed (or reciprocally halving the transistor resistance) by a factor of X will require increasing voltage by only sqrt(X), at least in the efficient part of the voltage/frequency curve.

As for finfets Vths they are not lower than planar, the difference is that finfets are technically multigate devices that allow both better conduction when switched on and lower leakage when transistors are switched off, this is independant of the Vth itself and has its source in the multiple gating.

The RVT, HVT and LVT distinction is the same for both process in the limits of the process characteristics, wether it s planar or Finfet a LVT device is a low Vth device whose role is to switch faster but at the expense of (much) more leakage, FTR leakage variation from RVT to sLVT should be something like 10^6, so it s obvious that a design cant use only fast transistors, it would be useless anyway for most part of the circuitry.

 

[bjt2]

I know the theory... I was searching on google and didn't find actual numbers, so i was asking you for the actual VTh... I read somewere that below 0.4-0.5V of VDD you can't go, so i was assuming a Vth in the ballpark of this, but i would really know. I also think that sLVT 14nm FF transistor has lower Vth than a LVT 28nm...

Anyway in mi search, found some images that confirms your statement of higher parasitic capacitance (understandable, since the gate is multiple, so bigger), but the increment is more than offset by one node, let alone two as in the AMD case...

Calculating the slope of dynamic power/GHz in the NEON test chip of 2 years ago I found, at the time, a big advantage (220mW for 1.1GHz for 28nm, plus 110mW of leakage and 310mW for 2.41GHz, plus 18mW of leakage for 14nm FF, both with LVT transistors, both with 330mW total power) on the 14nmFF PLUS 1/6 of leakage... I don't know if this is all due to transconductance, capacitance or Vth, but this is an HUGE gain...​

 

[Abwx]

I know the theory... I was searching on google and didn't find actual numbers, so i was asking you for the actual VTh... I read somewere that below 0.4-0.5V of VDD you can't go, so i was assuming a Vth in the ballpark of this, but i would really know. I also think that sLVT 14nm FF transistor has lower Vth than a LVT 28nm...​

Vth is in the 0.15-0.5V range, the higher Vth transistors (because there are different kinds in a design) will dictate the minimum voltage, hence the values you re quoting.

Anyway in mi search, found some images that confirms your statement of higher parasitic capacitance (understandable, since the gate is multiple, so bigger), but the increment is more than offset by one node, let alone two as in the AMD case...

I pointed that node shrink compensate for the higher capacitance, without this shrink finfets would be irrelevant, FI w GF s 14nm LPP has only 20% lower capacitance than their 28nm HP despite roughly a full node shrink.

Calculating the slope of dynamic power/GHz in the NEON test chip of 2 years ago I found, at the time, a big advantage (220mW for 1.1GHz for 28nm, plus 110mW of leakage and 310mW for 2.41GHz, plus 18mW of leakage for 14nm FF, both with LVT transistors, both with 330mW total power) on the 14nmFF PLUS 1/6 of leakage... I don't know if this is all due to transconductance, capacitance or Vth, but this is an HUGE gain...

What are the respective voltages for 28nm and 14nm..?.

And whose foundrie s process is it exactly..?

 

[bjt2]

Vth is in the 0.15-0.5V range, the higher Vth transistors (because there are different kinds in a design) will dictate the minimum voltage, hence the values you re quoting.



I pointed that node shrink compensate for the higher capacitance, without this shrink finfets would be irrelevant, FI w GF s 14nm LPP has only 20% lower capacitance than their 28nm HP despite roughly a full node shrink.


​

What are the respective voltages for 28nm and 14nm..?.

And whose foundrie s process is it exactly..?

I quoted only the most performant process, there was also the SHP, that didn't reach the 330mW... The 28nm is the 28nm BULK HPP (i think GF) and the 14nm is the 14nm LPP of samsung/GF... I quoted the LVT vs LVT. There was also RVT implementation... 0.8V nominal for the 14nm and 0.85V for the 28nm. At -10% the chip must still work and the power is measured at +10% @125Celsius

I can't find anymore the webinar slides, it was posted here a while ago... But the youtube video is still here... At 37:00 there is what i am saying: https://www.youtube.com/watch?v=wwa_GqU2LlQ

 

[AtenRa]

LOL, ain't nobody selling 5960X performance for $300.

Price follows performance. Period.

True for the $300 but it shouldn't be more than $600 (if it is close to 5960X) for a 2017 product.

 

[coercitiv]

LOL, ain't nobody selling 5960X performance for $300.

True for the $300 but it shouldn't be more than $600 (if it is close to 5960X) for a 2017 product.

Since we're all making predictions, I see Zen 8c priced competitively against Skylake X 6c, not the 8c variant. Whether that will be a tad higher or lower, it will depend on how high both chips can clock.

How much is a 6c Broadwell right now, $430? Let's call it an optimistic $400 for Zen, with oc potential in the 4Ghz+ area.

 

[AtenRa]

How much is a 6c Broadwell right now, $430? Let's call it an optimistic $400 for Zen, with oc potential in the 4Ghz+ area.

Core i7 6850K is 6C 12T at $600