AMD Ryzen (Summit Ridge) Benchmarks Thread (use new thread)

[krumme]

The stock market seems to be excited by this news.

I'm going to stay cautiously optimistic, but it could be that AMD is at least on their way to being a realistic alternative Vs. bottom dollar budget parts.

Fingers crossed we see something awesome in 2017. I'd love to see AMD come back alive and duke it out with Intel like we saw during the MHz wars in the late 90's.

The stock market hears a confident Lisa and saw a [Removed Vulgar] server motherboard fit for 64 cores. Thats about the complexity of information they need to push the botton and use a few M and go to next situation. They dont care for gamers and old desktop nerds on anandtech

NO PROFANITY ALLOWED IN TECH
Moderator Aigo

 

[sirmo]

I don't know about anyone else but I want my next laptop to sport Zen + GCN + HBM2

 

[Phynaz]

I find this slide interesting

The story it tells is the efficency gains over Excavator are all due to the IPC uplift. This chart says power consumption of Zen is the same as Excavator (depending upon AMD's definition of "Energy per Cycle" of course).

So 95W Zen quads at 3.7 - 4.0 Ghz. Anybody want to extrapolate Octacore clocks from that?

 

[lifeblood]

It can't hit a 3.5ghz wall. There's just no way. They had to know that wouldn't work and that they'd just get laughed at by PC enthusiasts and gamers...

Unfortunately the maximum clock is in many ways controlled by the manufacturing process. If GloFo can't deliver the clocks then AMD can't do much about it. And I bet that's the real issue right now. The Broadwell Blender video and the leaked ES sample results we've been dissecting shows that IPC improvements are good. Everything now rests on the final clock speeds and price.

I wonder if the delay until 2017 is in order to give GloFo more time to improve their still immature process? Processes get better with time, with the biggest efficiency improvements usually coming early in its lifespan. A delay of only a few months could result in some relatively big gains in efficiency (or usable chips). Maybe 3.2ghz is the max clock possible today, but in a few months 3.5ghz might be obtainable. If that's the case than AMD needs to delay. Too much is riding on a succesful Zen launch. They need to put their best foot forward from the beginning.

 

[Erenhardt]

I find this slide interesting

The story it tells is the efficency gains over Excavator are all due to the IPC uplift. This chart says power consumption of Zen is the same as Excavator (depending upon AMD's definition of "Energy per Cycle" of course).

So 95W Zen quads at 3.7 - 4.0 Ghz. Anybody want to extrapolate Octacore clocks from that?

You may use 95W Piledriver E SKUs. I don't think there is a lot between them and if there is, we only setup us for a nice surprise. 3.2-3.3 base and 4.0-4.2 turbo

 

[raghu78]

It can't hit a 3.5ghz wall. There's just no way. They had to know that wouldn't work and that they'd just get laughed at by PC enthusiasts and gamers. The enthusiasts are very important. They are the ones who praise the hardware and spread the word about the CPU to the general public. The enthusiasts are the ones who set the tone for whether or not the product is good for everyone else. Servers are a different thing and you don't hear people praising server performance publically very much. Its not exciting and most consumers don't care. If 3.5ghz is what they need to succeed in the server department, then good for them. They will fail on the desktop with clocks like that. And I do mean fail. If the CPU can't be OC'd past 3.5ghz or so, it will be seen as weak. Its practical performance will be limited to what we've already had since 2010.
I have more faith in AMD. I think Zen will be a good clocker and will pass the 4ghz mark with regularity. I think it will do well with water.

You need to look at it from AMD's perspective . What were the goals for Zen ? To help AMD get back into the lucrative x86 server market. Intel's most profitable division is their Data Center group with roughly 15+ billion dollars of revenue and almost 100% x86 server market share. AMD require 20-25% market share in servers to be a sustainable business as they have huge debts to pay off first. Enthusiast desktops don't bring anywhere close to even 50% of server revenues. AMD's plan seems to have been to go for maximum throughput (with lots of cores) and have competitive single thread performance in servers. High core count servers rarely clock to above 3.5+ Ghz even under turbo.

http://www.anandtech.com/show/10158/the-intel-xeon-e5-v4-review/6

AMD Carrizo which used 28nm with High Density Libraries topped out at 3.5 Ghz. With Bristol Ridge for desktops which launched recently the clocks went upto 4.2 Ghz on the A12-9800. So we will see Zen initially start out at 3.5 Ghz clocks (which should be good enough for servers when turboing) and then the second iteration Zen+ would probably hit 4+ Ghz in early 2018 (along with IPC improvements) . I also think GF 14nm would be mature enough to hit 4 Ghz (with reasonable power increase) by late 2017/early 2018.

 

[inf64]

Anyone noticed that most tech sites cite 8MB of L3 for the whole chip while the 8C part should be having 16MB of LLC (8MB of L3 per "unit" where unit is a group of 4 cores)?

 

[Abwx]

In those Zen related slides there s this one :

So Finfets used for Zen not only consume less but also have higher working frequency in respect of a 28nm that can only be the one used for Kaveri/Carrizo/Bristol Ridge.

 

[krumme]

I find this slide interesting

The story it tells is the efficency gains over Excavator are all due to the IPC uplift. This chart says power consumption of Zen is the same as Excavator (depending upon AMD's definition of "Energy per Cycle" of course).

So 95W Zen quads at 3.7 - 4.0 Ghz. Anybody want to extrapolate Octacore clocks from that?

Its a graph without x and y axis ! Wtf !!! Lol. Its the most insane ppt ever - its defying conventions. What is energy per clock cycle?. Is that normalized within 32nm process node or what. Lol. Crazy stuff.

But hey. The basic good news here is great news.
Its confirmed (claimed) its 40% uplift vs excavator. And not piledriver. Thats huge imo and bodes very well for the long run. Great.

 

[Insert_Nickname]

AMD Carrizo which used 28nm with High Density Libraries topped out at 3.5 Ghz.

3.8GHz. My 845 runs just fine at that. No issues with throttling whatsoever.

 

[Phynaz]

You may use 95W Piledriver E SKUs. I don't think there is a lot between them and if there is, we only setup us for a nice surprise. 3.2-3.3 base and 4.0-4.2 turbo

What we know:

Zen TDP = 95W (? for quads)
Excavator TPD = 95W
Zen pwr/clock = Excavator pwr/clock

Therefore Zen clock = Excavator clock.

Yes, I'm leaving the APU section power draw out.

So the question is, does Excavators' rated TDP apply to CPU only loads?

 

[Sweepr]

For those who wants to verify that Blender use different code on AMD and Intel,install GIT & follow the instructions

https://t.co/z6lV5faHxw

 

[Abwx]

Its a graph without x and y axis !

What matter is that it show that the Finfet top at higher frequency than 28nm and at a lower power.

Beside the shape of the curves say that the scale is linear and start at 0 for both power and frequency....

 

[inf64]

Oh yes the FPiodnel strikes back. Conspiracy galore, took him long enough...

 

[Nothingness]

The clown is back. Piednoel has long lost credibility, he's now just an Intel marketing droid.

Read the whole Twitter discussion. What he says in this case is so stupid: the only difference seems to be that the code check cache sizes depending on CPU ID and adapts to it. And then he says that code that adapts to cache hierarchy can't be used to compare IPC. Hilarious.

 

[Glo.]

The clown is back. Piednoel has long lost credibility, he's now just an Intel marketing droid.

Read the whole Twitter discussion. What he says in this case is so stupid: the only difference seems to be that the code check cache sizes depending on CPU ID and adapts to it. And then he says that code that adapts to cache hierarchy can't be used to compare IPC. Hilarious.

Reposting that "stupidity" here is just repeating his FUD.

 

[Bryf50]

He's so wrong it's embarrassing. AMD doesn't even stand for Advanced Micro Devices in that picture.

Matlab equivalents:
http://www.mathworks.com/help/matlab/ref/amd.html

http://www.mathworks.com/help/matlab/ref/colamd.html

 

[sirmo]

He's so wrong it's embarrassing. AMD doesn't even stand for Advanced Micro Devices in that picture.

Matlab equivalents:
http://www.mathworks.com/help/matlab/ref/amd.html

http://www.mathworks.com/help/matlab/ref/colamd.html

Concrete proof that he has no idea what he's looking at. He's just looking for anything to fit his narrative.

Luckly Blender is fully open source. It doesn't get more transparent than that. If AMD were going to cheat they wouldn't do it with an open source project.

 

[inf64]

LMAO he deleted the tweets once he got exposed in the comments . Wow just wow, a new low for Francois Piednoel. And we thought he had reached the lowest point, bam! he proves us wrong

 

[SketchMaster]

LMAO he deleted the tweets once he got exposed in the comments . Wow just wow, a new low for Francois Piednoel. And we thought he had reached the lowest point, bam! he proves us wrong

Poor guy.

Removed Picture.

Guys stop posting irrelevant gif's / pictures in this thread.
I am getting tired of removing them.

And once again STAY ON TOPIC... this post is treading a gray line which i am giving my last warning to.

Keep on topic in regards to ZEN or just DONT POST AT ALL in this thread.

Moderator Aigo.

 

[The Stilt]

- L2 latency
- L3 latency

- Noon
- The ordinal of brom (Br)

Quite Hounds-ish.

Allegedly.

 

[DrMrLordX]

I'm still interested in seeing if Summit Ridge has that limited AM4 release in 2016. I like to see things like that Blender bench 'cuz that shows Summit Ridge to be strong not just in ST IPC but in throughput, which is definitely one area where it needed to deliver.

2017 is where the important things happen, though.

So how efficient can Intel get their Broadwell Xeon products in the 3 GHz range? We don't know where those 32c/64t Zeppelin parts will be clocked, nor do we necessarily know TDPs, but Intel has products like the Xeon-D 1540 with TDP 45W and 2 GHz base/2.6 GHZ turbo 8c/16t (with extra stuff on-die). They've had that since Q1 2015 according to launch date anyway.

Can Zeppelin get as low as 45W TDP within that clockspeed range using an 8c/16t part?

 

[F-Rex]

Si ipc is around broadwell which is better than expected ( depending on who you asked hère zen ipc was expected anywhere between Sandy and haswell). So we are left with shipping frequencies.
Some said 2.8/3.2 would be the top frequencies. They are already wrong because amd Said it Will be higher than 3...

Question: how Intel let it happen?

 

[The Stilt]

Isn't 3.2GHz > 3.0GHz?

 

[blublub]

Isn't 3.2GHz > 3.0GHz?

He was referrong to base clock which was 2.8 on the leaks with AotS and was 3.0 on AMDs ES yesterday with hint of further increases