From a high level view and based on what Hot Chips slides revealed, Zen is somewhere in between SB and Skylake when core resources are in question (closer to Skylake in integer and closer to SB/IB in FP). I bet the IPC will end up right in the middle of these two and from AT we know the gap is around 25%. So if it was to end up in the middle of that range or a bit lower (around 10% faster than SB) it would end up being: 1) just a tiny bit faster than IB (~4%) ; 2) 7% slower than HSWL; 3) 10% slower than BDWL ; 4) ~14% slower than Skylake (funny enough the int/fp schedulers in Zen are ~15-20% smaller than Skylake's and right at Haswell level).
A bit off-topic, but at the time, attempting to use a tilde produced a dash instead (~~~~~ see it's still doing it) so . . . must be a bug/snafu in there somewhere. Anyway I think VirtualLarry caught on to it.
sigh..... lets think about this a second.Even when compiled with ICL, the SMT yield in Blender is abnormally high. Combined with the fact that the AVX2 kernel seems to do nothing, I don't think Blender manages to extract all of the performance potential out of Haswell and newer Intel parts.
Tomorrow morning I'll upload all of the builds I compiled today, so other people can test them too.
OT, but I saw tildes in my post, and I see them in yours. Check your font, your browser zoom factor, and your screen scaling and cleartype settings.
Even when compiled with ICL, the SMT yield in Blender is abnormally high. Combined with the fact that the AVX2 kernel seems to do nothing, I don't think Blender manages to extract all of the performance potential out of Haswell and newer Intel parts.
sigh..... lets think about this a second.
1. AVX2 is really just(mainly,mostly) an int SIMD instruction set ( you know like MMX)
For existing vectorized code that uses floating point operations, you can gain a potential performance boost when running on newer platforms such as the Intel® Xeon® processor E5 v3 family by doing one of the following:
- Recompile your code, using the Intel® compiler with the proper AVX2 switch to convert existing SSE code. See the Intel® Compiler Options for Intel® SSE and Intel® AVX generation (SSE2, SSE3, SSSE3, ATOM_SSSE3, SSE4.1, SSE4.2, ATOM_SSE4.2, AVX, AVX2) and processor-specific optimizations for more details.
- Modify your code's function calls to leverage the Intel® Math Kernel Libraries (Intel® MKL) which are already optimized to use AVX2 where supported
- Use the AVX2 intrinsic instructions. For high level language (such as C or C++) developers, you can use Intel® Intrinsic instructions to make the call and recompile code. See the Intel® Intrinsic Guide and Intel® 64 and IA-32 Architectures Optimization Reference Manual for more details
- Code in assembly instructions directly. For low level language (such as assembly) developers, you can use those equivalent AVX2 instructions from their existing SSE code. See the Intel® 64 and IA-32 Architectures Optimization Reference Manual for more details
That AMD specially selected blender for a reason instead of using an proven generally accepted benchmark?sigh..... lets think about this a second.
1. AVX2 is really just(mainly,mostly) an int SIMD instruction set ( you know like MMX) so whats the workload look like, blender is rendering right? 3D co-ord space right? FLOATING POINT right?
2. both cores appear to get a massive boost from SMT, what does that tell you? Lots of cache misses/execution bubbles. Making those cases better is exactly how you improve IPC.....
So how isn't it using all of Haswell and newer iIntel parts potential. You seem to do all this good methodical work and then jump the shark at the easy part....................
Today I spent (too) many hours while testing Blender.
I made few customized builds including the standard MSVC 2013 compiled version, with and without AVX2 and then a similar set of builds with Cycles compiled with ICL. It soon became obvious that despite Blender does have AVX2 kernel present, it does absolutely nothing (at least speed wise). The AVX2 kernel can be disabled easily during build time (CCX_HAS_AVX2 = False) and disabling it didn't change the performance even the slightest neither on MSVC or ICL. The funniest thing is that compiling Cycles with ICL generic arch tunings (SSE2, SSE3, SSE4.1 & AVX) improved the performance on Piledriver by ~ 39%. Meanwhile the performance on Haswell-E improved by < 9%. So much for the ICL making AMD CPUs look worse than they actually are
Even when compiled with ICL, the SMT yield in Blender is abnormally high. Combined with the fact that the AVX2 kernel seems to do nothing, I don't think Blender manages to extract all of the performance potential out of Haswell and newer Intel parts.
Tomorrow morning I'll upload all of the builds I compiled today, so other people can test them too.
There isn't much need for Intel to do this at this time, given that the FX chips are so old now.The Stilt said:So much for the ICL making AMD CPUs look worse than they actually are
Wouldn't XOP/FMA3-4 support improve the performance further, provided that the program would be coded to leverage it?The Stilt said:(SSE2, SSE3, SSE4.1 & AVX)
On ST I agree... on MT... I don't think so....It's virtually impossible for Zen to be faster than broadwell. Why? Because AMD basically outright said it won't be..
40% higher 'ipc' than Excavator is less than Broadwell.. Simple
If you watch the video of Blender Video, AMD themselves essentially state that it shows what it's capable of. T
There's enough Architectural differences (creating strength's and weaknesses) to [almost] ensure there will be corner cases of Haswell-broadwell throughput (more so than ST IPC), especially given there are areas where Zen is already technically at an advantage.. but on average - No, obviously not.
How IPC gets increased, also depends on the uarch feature's metrics (area, delay, perf increase/power increase). So it might be more expensive to try to avoid the bubbles and misses, than to add more resources, which improve performance in general. Some misses/bubbles are just inevitable, as long as 2GB L1s are out of question. SMT then just becomes the add-on to make use of the resources during stalls of the other thread.2. both cores appear to get a massive boost from SMT, what does that tell you? Lots of cache misses/execution bubbles. Making those cases better is exactly how you improve IPC.....
It's virtually impossible for Zen to be faster than broadwell. Why? Because AMD basically outright said it won't be..
40% higher 'ipc' than Excavator is less than Broadwell.. Simple
If you watch the video of Blender Video, AMD themselves essentially state that it shows what it's capable of. T
There's enough Architectural differences (creating strength's and weaknesses) to [almost] ensure there will be corner cases of Haswell-broadwell throughput (more so than ST IPC), especially given there are areas where Zen is already technically at an advantage.. but on average - No, obviously not.
How IPC gets increased, also depends on the uarch feature's metrics (area, delay, perf increase/power increase). So it might be more expensive to try to avoid the bubbles and misses, than to add more resources, which improve performance in general. Some misses/bubbles are just inevitable, as long as 2GB L1s are out of question. SMT then just becomes the add-on to make use of the resources during stalls of the other thread.
Yes, AMD likely chose one of the best comparisons to show the best of Zen's capabilities. Nothing so far raises expectations beyond IB like IPC on average given AMD's 40% statements.
The Blender builds from yesterday (four builds, 241MB in total).
https://1drv.ms/u/s!Ag6oE4SOsCmDhEHafXXr3vrRqo-N
And how exactly did you come to those conclusions?
Since when did fp workloads show AMD in the best possible light?
And how do you conclude that Zen/Summit Ridge is going to have "IB like IPC" when one of two available benchmarks shows it slightly edging out Broadwell-E in overall throughput? Remember, Zen is not a CMT design.
As a developer, it's pretty damn easy to sneak in a few instructions that would cripple certain architectures.
I've seen the Zen circle at local shops already. But it might look like sth. different to people with a predefined opinion.
Really now? Some examples, please.
Any instruction that has a higher probability of a cache-miss or targeting FPU registers in a fixed-size, nonparallel manner. Also, targeting a vendor-specific instruction set (also in a fixed length if it is common) can drastically alter performance. Does SSE/3DNow! ring a bell for anyone? This isn't rocket science.