But that's exactly what AMD tried with Bulldozer. Zen was touted was a high IPC architecture to go head to head with Intel.The main selling point for SR may be multithreaded performance per $.
But that's exactly what AMD tried with Bulldozer. Zen was touted was a high IPC architecture to go head to head with Intel.
But still not enough. It's as if Intel was also offering a 14nm Sandy Bridge SKU. Sure, if the price is low enough they will sell some units.its a lot higher than XV!
IPC is a mean, and that's what I expect to be used when more applications are involved to calculate some "aggregated" IPC.AMD didn't say if the 40% was minimum, mean, maximum, but looking at blender, the maximum is at least +80%. This imply that 40% at least is the mean value, that is reasonable. Stating that 40% is the minimum in an official statement is very dangerous, because a single example of less than 40% gain would suffice to be wrong.
Thinking better on this subject, i think (and probabily can be verified lokking at the small notes) that AMD intended mean IPC, as it is reasonable.
Well, even emulators have loops, and a bigger loop (the main, "evaluation", loop at least), but it doesn't mean that a uop cache can be of any benefit.In the case of Zen you can safely assume a weighted mean between 4 and 6 upos/cycle, weighted by the uop cache hit/miss ratio. Because if there is a branch misprediction, the uops can still be taken on the uop cache, so if there is an hit, the throughput is still 6 uops/cycle.
You don't need the decoder again, except if the branch is in a never taken piece of code... But we are talking of loops here, right? Because a single path without loops has a negligible execution time, compared to loops of code and so in the total performance evaluation can be safely ignored. We are talking of program that take at least seconds to be executed, so piece of code executed only one time and first execution of a loop, were the uop cache probabily would miss, are a negligile fraction of the total execution time...
Discussions about IPC are perfectly in-topic. Ignore them if you don't like, but don't invoke censorship.Geez, 74 pages and 73 of them are special friends ELF and Cidimauro arguing about what "40%" means, as if that has any bearing on current zen performance whatsoever. Can we give these trolls their own thread to fill with this drivel? It's pedantic and totally unrelated to technology, it's also threadcrapping at this point.
The slide talks about core improvements, so I agree with you that it should be referred to SMT.I expected 40% to be the minimum actually, and I have seen it quoted somewhere here, but when searching I could not find a direct reference, except:
First point suggests pretty clearly that 40% is with the SMT. Otherwise why list it under how the 40% IPC is gained?
Going off HotChips, I'd say it's IPC pretty clearly, and that means per core. Not 40% performance.
Sent from HTC 10
(Opinions are own)
But that's exactly what AMD tried with Bulldozer. Zen was touted was a high IPC architecture to go head to head with Intel.
Well, even emulators have loops, and a bigger loop (the main, "evaluation", loop at least), but it doesn't mean that a uop cache can be of any benefit.
If you take a look at the main loop of an emulator, for example, you'll see a big (C-like) switch statement which usually is internally translated to an unconditional jump to a pointers table to execute the code of specific instructions. And so on with other switches for handling other cases, especially with more complex architectures to be emulated (x86 and 68K are primary examples, with the latter which is even more complicated due to 16-bit opcodes).
Virtual machines for programming languages have very similar behaviors.
https://www.heise.de/newsticker/mel...enCompute-mit-ROCm-aber-kein-Zen-3491050.html
- No samples were presented/showcased at SC16 conference, not even behind the public
- In NDA sessions only slides were presented
- In SPECint2006 AMD replaced Intel with gcc compiler and the performance for 32 core Naples was slightly below Haswell
- Results are without Hyper-Threading because of somes issues
- When all is working AMD claims they will be on par with Skylake EP (Xeon E5 2698v5), but there is no info on what this is based on or if this is even based on some real comparisons rather than predictions, also AMD remained silent about some other important HPC performance metrics (e.g. SPECfp, Linpack)
They didn't say which Haswell was used but given that Haswell maxed out at 16 or 18 cores, it doesn't sound great because Skylake will be a different tier with up to 28 cores or 32 cores for Custom SKUs. To me it sounds suspicious, the silence/issues/lack of samples etc.
- In SPECint2006 AMD replaced Intel with gcc compiler and the performance for 32 core Naples was slightly below Haswell
https://www.heise.de/newsticker/mel...enCompute-mit-ROCm-aber-kein-Zen-3491050.html
- No samples were presented/showcased at SC16 conference, not even behind the public
- In NDA sessions only slides were presented
- In SPECint2006 AMD replaced Intel with gcc compiler and the performance for 32 core Naples was slightly below Haswell
- Results are without Hyper-Threading because of somes issues
- When all is working AMD claims they will be on par with Skylake EP (Xeon E5 2698v5), but there is no info on what this is based on or if this is even based on some real comparisons rather than predictions, also AMD remained silent about some other important HPC performance metrics (e.g. SPECfp, Linpack)
They didn't say which Haswell was used but given that Haswell maxed out at 16 or 18 cores, it doesn't sound great because Skylake will be a different tier with up to 28 cores or 32 cores for Custom SKUs. To me it sounds suspicious, the silence/issues/lack of samples etc.
The slide talks about core improvements, so I agree with you that it should be referred to SMT.
Which is obvious, considering how a core works (it commits instructions which come from ANY thread), and the definition of IPC.
And I still think that it's completely non-sense talking of "ST IPC", unless you are measuring a purely ST application (in which case they match): a MT application will use BOTH (in a SMT-2 design) hardware threads to achieve the goal, and so the core will execute/commit instructions of BOTH threads.
P.S. I know that, after the presentation, an AMD executive talked about "ST IPC" for the +40%.
Currently, in the big datacentres of Europe, the main Virtualized and Cloud infrastructure... I've seen none using AMD chips. As sad as that sounds.Bulldozer was also an efficiency disaster, while Zen could be alright. Could still be alright for servers and laptops (i.e. where the money is), even if it doesn't clock high enough to win high end desktops.
Replacing icc with gcc is the way to go to make fair comparisons for SPEC given how Intel tuned their compiler for that benchmark.- In SPECint2006 AMD replaced Intel with gcc compiler and the performance for 32 core Naples was slightly below Haswell
It was my understanding that AMD isn't aiming at HPC. Anyway they don't stand a chance against upcoming AVX-512 Xeon CPU (unless Intel has to drastically reduce frequency when running AVX-512 code).also AMD remained silent about some other important HPC performance metrics (e.g. SPECfp, Linpack)
Yes, bad feeling here tooThey didn't say which Haswell was used but given that Haswell maxed out at 16 or 18 cores, it doesn't sound great because Skylake will be a different tier with up to 28 cores or 32 cores for Custom SKUs. To me it sounds suspicious, the silence/issues/lack of samples etc.
Comparing vs Haswell is a move that makes sure of the fact that they have a product that is noncompetitive with Intel 2014, 2015, 2016, 2017. There's problems, for sure. My alarm bells are now exploding :/https://www.heise.de/newsticker/mel...enCompute-mit-ROCm-aber-kein-Zen-3491050.html
- No samples were presented/showcased at SC16 conference, not even behind the public
- In NDA sessions only slides were presented
- In SPECint2006 AMD replaced Intel with gcc compiler and the performance for 32 core Naples was slightly below Haswell
- Results are without Hyper-Threading because of somes issues
- When all is working AMD claims they will be on par with Skylake EP (Xeon E5 2698v5), but there is no info on what this is based on or if this is even based on some real comparisons rather than predictions, also AMD remained silent about some other important HPC performance metrics (e.g. SPECfp, Linpack)
They didn't say which Haswell was used but given that Haswell maxed out at 16 or 18 cores, it doesn't sound great because Skylake will be a different tier with up to 28 cores or 32 cores for Custom SKUs. To me it sounds suspicious, the silence/issues/lack of samples etc.
The information about SMT disabled because of a bug is exactly in line with information posted on carbonite forum few weeks ago, and largely concluded as being faked.
Comparing vs Haswell is a move that makes sure of the fact that they have a product that is noncompetitive with Intel 2014, 2015, 2016, 2017. There's problems, for sure. My alarm bells are now exploding :/
Sent from HTC 10
(Opinions are own)
Bulldozer was also an efficiency disaster, while Zen could be alright. Could still be alright for servers and laptops (i.e. where the money is), even if it doesn't clock high enough to win high end desktops.
We don't know, but the only truly positive message we have had was that Blender demo with all that associates with it. Others were either mixed, like that "leak" (or made-up BS, that it looks like) or straight negative (those geekbench leaks, that AotS leak, that article).So Zen is a bust? It's good? I'm getting conflicting messages here.
So Zen is a bust? It's good? I'm getting conflicting messages here.