Dunno for ST perf but throughput wise, i expect 80 % on average in Integer and more than 100% in FP, assuming 30% SMT gain this would imply about 40% and 55% gain in INT and FP respectively for ST.
Thanks. It's first time I see 'Energy per Cycle' statement. Looks like Zen has similar pipeline stage and FO4 delay compared to EXV, while have much wider engine and SMT.
This could also imply the IPC gain might be optimistic although still couldn't tell how much.
What you do need to be careful about is in assuming that this efficiency improvement applies at all frequencies.
Improvement is indeed at all frequencies, that s what "same energy/cycle" means...
It is written same energy per cycle, wich is clock cycle...
40% more instruction/cycle at same energy per cycle.
Do you think that Zen will consume less energy per cycle at 5GHz on 14LPP than Piledriver on the exotic 32nm SOI process did at 5GHz?
28nm + HDL enabled Carrizo to be much more efficient than Steamroller on 28nm (no HDL) within a given frequency range. Outside of that range, the efficiency gains evaporated and even reversed.
Because this is a PR slide, i wouldnt take it technically. It does says "for illustrative purposes only" after all.
I have a feeling this slide doesnt mean that ZEN will operate at the same clocks as EXV.
It means that at frequencies at wich it will operate it will consume the same as EXV at this very same frequency, dunno what is difficult to grasp here...
Yes the slide does saying it will consume the same as EXV at the same frequency, what it doesnt say is that ZEN will be able to reach the same Fmax
It also doesnt say, if both have the same Fmax that they will consume the same at that frequency.
Since we dont have the Frequency/Power diagram schematics for both the 28nm HDL and 14nm LPP , we cannot say anything about clocks/power at this stage.
That s answered in the slide i posted above , we have it, it s plainly displayed, the comparison is between the 28nm used for EXV and 14nm used for Zen the way it work for Zen, you think that they pulled random curves between random processes and chips to be displayed at HC, that is, at an enginers dedicated event..?.
Em,no.
In this slide they state that they reach as high frequency than with their previous process but at a fraction of the power.
Looking at the shape of the curves the vertical and horizontal scales are linear, the power efficency gain is the ratio of the curves abscissas, we can see that at max frequency power is about halved..
- For low frequency products. For high frequency products I see the two curves converge. It is a mobile process, like all the others. Meh.In this slide they state that they reach as high frequency than with their previous process but at a fraction of the power.
Yes. It means same power consumption at *ONE PARTICULAR* clock.
+40% IPC at equal energy per cycle means same consumption at same clock...
The line below is the energy spent per clock cycle...I have no idea how you got from that graph to "it will have the same clock speeds as Bulldozer"
They said that Zen was maintaining the expectations in october 2015 and recently at hotchips.Thanks. It's first time I see 'Energy per Cycle' statement. Looks like Zen has similar pipeline stage and FO4 delay compared to EXV, while have much wider engine and SMT.
This could also imply the IPC gain might be optimistic although still couldn't tell how much.
Yes. It means same power consumption at *ONE PARTICULAR* clock.
At what clock? With one core? Which parts were measured? 1GHz vs 1GHz core?
PR is PR is vague.
Theyre also suggesting lower power usage as the Core?CPUs? have progressed, and they are showing a major drop in energy consumption with Zen.
Again, clock, load, for which blocks or the whole CPU, and if so which CPU, totally unknown.
That's a typical new process vs old process compare. Says *nothing* about clock or process prowess except that the power profile and IPC has improved.
For power, this is what I'd like to see, as shown for Carrizo.
Sent from HTC 10
(Opinions are own)
Do you think that Zen will consume less energy per cycle at 5GHz on 14LPP than Piledriver on the exotic 32nm SOI process did at 5GHz?
I also encourage you to review this slide:
28nm + HDL enabled Carrizo to be much more efficient than Steamroller on 28nm (no HDL) within a given frequency range. Outside of that range, the efficiency gains evaporated and even reversed.
Yes the slide does saying it will consume the same as EXV at the same frequency, what it doesnt say is that ZEN will be able to reach the same Fmax
It also doesnt say, if both have the same Fmax that they will consume the same at that frequency.
Since we dont have the Frequency/Power diagram schematics for both the 28nm HDL and 14nm LPP , we cannot say anything about clocks/power at this stage.
We know for sure (official statement) that Zen integer pipeline length is 19 stages.And there's no data about Zen's FO4 and fMax. As well as there's no clear information about XV's number of stages.
So, no comparison can be made for such variables, and no conclusion can be made, as well.
What excavator part reaches 4GHz base and 4.3GHz turbo? I know that there are steamroller parts which can do that, but I've never heard of an excavator doing that.Despite that, excavator reach 4 base and 4.3 turbo at 95W and 4.8 in OC... Do you think that with 2 nodes and bulk vs finfet, this can't be beated? How was the gain of intel between 32nm BULK and 22nm FF?
- For low frequency products. For high frequency products I see the two curves converge. It is a mobile process, like all the others. Meh.
What excavator part reaches 4GHz base and 4.3GHz turbo? I know that there are steamroller parts which can do that, but I've never heard of an excavator doing that.
A10 7890K 4.1/4.3 (not 4), 95W... And it's not even excavator. But it's 4 core...What excavator part reaches 4GHz base and 4.3GHz turbo? I know that there are steamroller parts which can do that, but I've never heard of an excavator doing that.
A12-9800 is the fastest model available with 3.8GHz base, 4.2GHz boost.
Yes, and the situation hasn't changed: we don't know how many stages XV has. We don't know the FO4 of Zen. We don't know the fMax.We know for sure (official statement) that Zen integer pipeline length is 19 stages.
For XV we have a range of 15-20 and from Agner Fog's test we can estimate at most 20 stages (maximum branch mispredict penality), so we are in the same ballpark, at most, than excavator. We have already taken this subject in the past...