What most people still dont get is how one type of core or another is designed with a specific target in mind. It is correct that Cat family is smaller in die size than Dozer family, and they can achieve similar or lower power consumption at normalized clocks and voltages, and that IPC is the same at normalized clocks...
... See a pattern here? Yes, I have to say "at normalized" clocks every time I try to compare them in about anything valuable besides die size, because one product was designed to run at 3++Ghz, while the other at >2ghz clocks.
The problem here is that you are trying to compare them by lowering the Dozer family clocks (justifying a potential mobile scenario), making it a uncomfortable situation for that kind of uarch, because the dozer family intended to reach their IPS target via clocks. Can we compare them by overclocking the cat family to the dozer family range of clocks? Right now, we cant, and that only is enough to tell both designs are suited for different purposes.
That we are able to get mobile offerings from the big core family is only determined because it is a more flexible design, thanks to its higher xtor count and subsequent die size. When you throw more xtors at the problem, you can scale back your performance to reach a wider range of power envelopes, even at a better perf/watt that the lower xtor count, but higher clocked variant. With the small core we just can't, and this is such a limitation that it's not a coincidence that the latest releases of the cat family of cores have all being about squeezing every mhz out of the design without leaving the targeted power envelopes. In other words, trying to find ways to scale upwards.
The problem with the big core family is that they aren't focusing enough in improving it's IPC (after it has been proven time after time that the 6hz target clock is not coming anytime soon, even less from GF) lately, but there has been too many "diversions" in the middle to deal with (making it HSA compilant, steering a little from the pure CMT design to compensate the max ammount of cores being halved in their top end consumer products, etc) to just focus on better IPC. The fact that they are stuck on a bigger node doesnt help at all, either, as a key point into making the Intel Core design what it is today was a succession of incremental width upgrades after each node shrink. The dozer core family is really longing for a doubling in it's width right now (and by judging the TDP of the top Carrizo offering, I just dont really think it will be coming at all).