AMD: Success of small cores vs. big cores?

[mrmt]

AMD's CMT design really hasn't worked well at all. That is probably why he keeps criticizing it.

Neither SUN's.

 

[Fjodor2001]

Anyway, AMD will not use CMT in their next-gen x86 uarch according to this article that says:

"Based on the unofficial information, everything is going to change in the next micro-architecture that is in development by AMD. Development of a new high-performance general-purpose x86 core from Advanced Micro Devices is currently in development headed by Jim Keller, according to Expreview web-site.

Not a lot of details about the new micro-architecture are known at present. What is recognized for sure is that it will drop CMT in favour of some kind of SMT (something akin to Intel’s HyperThreading) technology to improve performance in both single-threaded and multi-threaded cases."

 

[Enigmoid]

What about die area? Do you save die area or do you end up using more die area than with conventional designs? And what about power consumption? Does the added complexity for the CMT design adds up power consumption? And what about power gating? Does the added complexity hinders power gating of the core or CMT is neutral on the subject? And cache and memory management? Does CMT adds complexity for memory and cache management or is CMT neutral here?

Die area can be saved, at least in AMD's implementation due to non-duplicated resources (ie the FPU and parts of the front end). Its very probable that for a single thread power consumption is significantly higher while using two threads will allow for lower (and optimized) power usage. This is again due to the shared nature of the resources. Using one core activates a lot of the front end and the FPU while using both threads on a module only really adds another integer core (the entire section) and some additional stress on the front end. Power gating I'm assuming will be more complex. For instance the front end must be large enough to feed the entire module running full throttle; with only one thread loaded you would have to figure out how to power gate certain sections without impacting performance, it is extremely unlikely that a single thread can ever saturate the front end. Thus you have to cleverly figure out how to power gate sections of the front end that are not going to be fully utilized (very wide) such as the branch predictor and fetch/prefetch. You do not have to power gate but power consumption will be higher. A CMT design is much more complex from a hardware standpoint as you need to design a much larger and more complex module where there is more room for error (bottlenecks).

I'm not too sure about cache but AMD has really poor cache performance.

 

[Blitzvogel]

I don't see why multiplatform developers shouldn't target many small x86 cores like they have to with ARM these days. Game developers have to make due with the Jaguar cores in the PS4 and Xbox One, which automatically sets a basic performance precedence for PC ports. Productivity programs still on a single core need to get with the times if they are in any way heavy. Can anyone give me an example of a modern "heavy" single thread program for PCs that is in use?