the idea about it being an apu comes from a march 2016 rumor that placed it on am4 - which cant route 4 memory channels signals afaik.Snowy Owl might be APU but aside from that yes it should be a server SKU (more or less) brought to consumer just like Intel HEDT is. In the end even Summit Ridge is a server die.
The interesting bit would be if the x399 platform is unlocked and it better be or there isn't a point to it.
Chilled water anyone?
I would assume 40+ PCIe lanes.If that is 3.1 GHz base and 3.6 GHz turbo - it going to be one heck of HEDT/Workstation CPU. Plus Quad channel RAM and, I would assume, 32 GP PCIe lanes.
I would assume 40+ PCIe lanes.
Sendt fra min SM-G928F med Tapatalk
If that is 3.1 GHz base and 3.6 GHz turbo - it going to be one heck of HEDT/Workstation CPU. Plus Quad channel RAM and, I would assume, 32 GP PCIe lanes.
I think that's a safe bet. The 32-core Naples processor is supposed to be 8-channel memory, 128 PCIe 3.0 lanes. A 16-core HEDT processor with quad channel support could potentially have up to 64 PCIe 3.0 lanes.
Unless I've missed something - for PCIe 3.0 there are 16 GP lanes, 4 lanes dedicated to NVMe and 4 lanes for the chipset. Did I miss something?
For the TDP, the turbo is actually low, but that depends on how it works (and whether and by how much it'll OC). Only one core in all 16? One in each die? One in each CCX (which is the way I woulda thunk it would have worked in the current processors)? On water you can get a 6950K over 4.5, and there's precious little difference between 16 cores at 3Ghz and 10 cores at 4.5Ghz even with perfect multithreaded scaling. Pricing will be AMD's main advantage unless clocks can rise pretty significantly without busting the power budget. Unfortunately for AMD, the pricing of the processor may well be of minimal concern if you're also sporting dual high-end video cards, dual 10 GbE, a Decklink 4k Extreme 12g (or similar acquisition card), high-end camera gear, etc. A decent pair of Schoeps can run you about what a 6950k costs....
It will be interesting to see what happens. I'm definitely interested in the possibility (both quad channel and pcie lanes), but the usefulness of higher clocks for workstation users should not be underestimated. AMD is hopefully already talking to high-end software providers (just like it is for game devs). I know Edius devs need a call
I don't think so, but hasn't this question been asked before about Naples?Unless I've missed something - for PCIe 3.0 there are 16 GP lanes, 4 lanes dedicated to NVMe and 4 lanes for the chipset. Did I miss something?
My estimate is they want it to clock as closely to the 1800x as possible at about ~200-225W max, 200 would be ideal.
I am not convinced they don't have 32 lanes per die. Even if they got only 24, they could make 40 usable, 4 for M.2 and 4 for the chipset.
CPC mentions that it's ES not QS because it means that specs can change. QS tend to be what ends up in retail. Hard to say if they add XFR here too.
Aside from that, they should have more than one SKU and hopefully they are unlocked.
My educated guess is that Zen has 48 physical lanes. Naples has 128 lanes coming out of the CPU in a 1P configuration, but that doesn't count communication between the four dies which uses the same infinity fabric infrastructure. In a 2P configuration 64 lanes per CPU go into communicating to the other socket, or 64/4 = 16 lanes per chip. It wouldn't make sense to dedicate more lanes. Since it wouldn't make sense to have less bandwidth for the processors within a socket compared to the processors outside of a socket, it's a logical assumption that each Zen chip in a Naples module has 16 lanes (or more) dedicated to inter-module communication.
Now why so few lanes are exposed on the consumer platform, I have no idea...
Well, that's a block diagram alright. I don't know where it came from. There are some oddities to it (i.e. the PCIe lanes and memory config).
Oh, and I think you posted two of the same pic.
Hmmm....
I edited it an hour ago to fix it, no idea why you are seeing the old version.
Where did those diagrams came from ??? any link/s ??
This has been around on Reddit for a while. The schematics is allegedly from ASUS.
https://www.reddit.com/r/Amd/comments/618blp/x399_and_x390_leak/
On water you can get a 6950K over 4.5