estarkey7
Member
- Nov 29, 2006
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Nah, they will use Samsung 7nm tech.
How do you know?Nah, they will use Samsung 7nm tech.
They have been using Samsung tech for pretty much everything, and they made a agreement with GF for them to be able to use "other fabs" which basically means, they can now use Samsung fabs to make stuff.How do you know?
Made at gf?
When?
Even server based cpu's seem's to be unlocked.
Nah, they will use Samsung 7nm tech.
Fastest Xeon? Not so fast!
The roadmap with Zen at 14nm and 14nm+ , Zen 2 at 7nm and Zen 3 at 7nm+ looks promising. I think this is how it will play out.
Zen - 14nm - H1 2017
Zen - 14nm+ - H1 2018
Zen 2- 7nm - H1 2019
Zen 3 - 7nm+ - H1 2020
Hopefully AMD can get Zen clocks to atleast 4.5 Ghz or higher with 14nm+ . Thats going to be the key before Zen 2 arrives at 7nm in 2019.
Didn't I say that Pinnacle Ridge would use regular Zen cores not Zen2?
But you also said Pinnacle Ridge would use the same 14LPP process. I think we are looking at a better process probably like what we saw from Intel 14 to Intel 14+. The improved process should allow Zen to overcome its most important limitation - clock speeds.
If you run a "FP" workload 20% of the time, why would you buy 4-8 GPUs that would sit idle most of the time? What Xeon E5/SP offer is flexibility to use the same system for many types of workloads.For FP the Skylake Xeons would be in a completely untouchable league. But for FP performance AMD is going to use Radeon Vega Instinct (4-8 GPUs per system).
Nothing is stopping you from using E5s or SPs in 1S configurations. 8 channel memory is useless without compute* performance, which Naples lacks, given that it doesn't have AVX, let alone AVX-512. In fact, the reason there are 8 memory channels is likely because each die on the package is essentially its own independent processor, making Naples essentially a 4S configuration per package. We all know how well 4S/8S Intel systems perform (poorly). For power efficiency and latency, Naples should really only have 4 memory channels, but the lack of a unified uncore makes it impossible.I think the big disruption is going to come from AMD bringing the entire feature set - 32C/64T max core count, 8 channel memory, 2TB memory support to 1S systems.
There has never been any restriction from Intel on using a 2S-capable CPU in 1S configuration.Intel has always artificially segmented the 1S and 2S markets by not selling the chips with higher core counts and memory channels in the 1S market and demanding higher prices on the higher core count chips which are only sold in 2S systems. AMD is going to basically exploit that artificial segmentation by Intel and deliver disruptive performance, core counts and memory support for 1S systems at much lower TCO. Long term AMD might force Intel to sell much higher core count chips in 1S systems and we could see 1S growing share against 2S in the overall server market.
AMD has historically been far more comfortable with NUMA and NUMA-like than Intel. The biggest problem in HPC is that you run out of memory much before you run out of compute. Not all workloads can be AVX accelerated either. Naples should do very well in I/O bound applications, of which there are many.If you run a "FP" workload 20% of the time, why would you buy 4-8 GPUs that would sit idle most of the time? What Xeon E5/SP offer is flexibility to use the same system for many types of workloads.
Nothing is stopping you from using E5s or SPs in 1S configurations. 8 channel memory is useless without compute* performance, which Naples lacks, given that it doesn't have AVX, let alone AVX-512. In fact, the reason there are 8 memory channels is likely because each die on the package is essentially its own independent processor, making Naples essentially a 4S configuration per package. We all know how well 4S/8S Intel systems perform (poorly). For power efficiency and latency, Naples should really only have 4 memory channels, but the lack of a unified uncore makes it impossible.
* As in throughput-computing (e.g. HPC).
There has never been any restriction from Intel on using a 2S-capable CPU in 1S configuration.
Naples will probably see some adoption (can't do worse than 0% market share), but Skylake-SP isn't going anywhere. AMD will have to deliver a better integrated chip that covers all usage scenarios for the successor to really succeed in the datacenter market. The real problem Naples has to overcome isn't Skylake-SP, but Xeon D. For running multiple instances of lightly threaded workloads, where the MCM/CCX overhead is avoided, Xeon D offers amazing cost effectiveness.
If you run a "FP" workload 20% of the time, why would you buy 4-8 GPUs that would sit idle most of the time? What Xeon E5/SP offer is flexibility to use the same system for many types of workloads.
Nothing is stopping you from using E5s or SPs in 1S configurations. 8 channel memory is useless without compute* performance, which Naples lacks, given that it doesn't have AVX, let alone AVX-512. In fact, the reason there are 8 memory channels is likely because each die on the package is essentially its own independent processor, making Naples essentially a 4S configuration per package. We all know how well 4S/8S Intel systems perform (poorly). For power efficiency and latency, Naples should really only have 4 memory channels, but the lack of a unified uncore makes it impossible.
* As in throughput-computing (e.g. HPC).
Naples will probably see some adoption (can't do worse than 0% market share), but Skylake-SP isn't going anywhere. AMD will have to deliver a better integrated chip that covers all usage scenarios for the successor to really succeed in the datacenter market.
Hmm, seems so, but, I don't follow their logic here.No they won't. In the Q&A an analyst asked what foundries is AMD going to use at 7nm, the answer was GF & TSMC. And no, GF won't use Samsung 7nm because they developed their own on top of IBM's.
Forrest "Datacenter leadership" !
That is a radical statement and priority
Naples should do very well in I/O bound applications, of which there are many.
It has nothing to do with GPUs being "faster". It makes no sense to buy extra hardware for a workload that you only run a fraction of the time. That's why you don't see datacenters being loaded up with GPUs, except in a few use cases. In addition, there are vectorized workloads that can't be run on GPUs, either because of control logic (video encoders) or memory requirements.Xeon will continue to have an advantage there. Intel knows that most customers don't like to transition to new platforms even if its much faster. Which is why they continue to use Xeon despite GPUs being faster. Because of that Intel keeps beefy FP units on board. Of course they know that can't be the sole defense against newcomers, which is why they have chips like Xeon Phi.*
I can't think of any workload that needs 300 GB/s of memory bandwidth yet isn't vectorized. You can't even access memory that quickly without using SIMD, other than through bulk memory copy.I think we shouldn't try to fit the world within one picture. There are of course scenarios where the extra memory bandwidth comes useful. Also because of those extra channels, their platform supports 33% more memory capacity than Intel as well(true against both Broadwell and Skylake). There are enough programs that aren't bound by vector unit performance but memory bandwidth.
If you really think Naples is 60% more energy efficient (32 * 3 / 180 vs 28 * 2.5 / 205) than Skylake, despite Zen drawing as much power as Broadwell-E, there's nothing to discuss.And relatively its power efficient enough. A 32 core AMD EPYC is at 180W with 8 memory channels, 64 PCIe lanes per CPU(if used in 2P) at probably near 3GHz clock speeds. That compares extremely favorably against Skylake SP, which is 28 cores, 205W, 6 memory channels, 48 PCIe lanes and 2.5GHz clocks. Dare I say Intel might need a rumored 32 core version if they want to keep the performance halo.
I expect to see Naples fail to reach wide adoption due to extreme NUMA overhead (2S * 4 die * 2 CCX, or 16 nodes to reach parity with Intel 2S platform).Ok, if you are definiting success as an overnight one where it starts taking 30% in the first year, sure, you are right. But that almost never happens. But it'll dent Intel's growth enough that their projections of datacenter having "high single digit growth" will disappear. And I've seen its in servers where in an extremely short time(1-2 years) 100% customers buy the latest generation CPUs. Because unlike in PCs where performance is "wanted", in servers its needed. So it can happen rapidly.
The roadmap with Zen at 14nm and 14nm+ , Zen 2 at 7nm and Zen 3 at 7nm+ looks promising. I think this is how it will play out.
Zen - 14nm - H1 2017
Zen - 14nm+ - H1 2018
Zen 2- 7nm - H1 2019
Zen 3 - 7nm+ - H1 2020
Hopefully AMD can get Zen clocks to atleast 4.5 Ghz or higher with 14nm+ . Thats going to be the key before Zen 2 arrives at 7nm in 2019.