I'm atheist. There is no sign of CMT in Zen.Well I still believe that amds SMT works just like their CMT so...
I mean 40% + (but how much ? ) over XV but 1/4 of that is senseMI it only works out if each core can be split into two ,slightly slower cores, but would then have almost perfect scaling in MT workloads.
Otherwise they will have to have achieved something like close to 100% IPC increase with better SMT Implementation than intel's HTT.
There's dreaming but then there's delusion as well.
Sys power includes other components, which have increased power consumption as well, even if just a few watts each.Hint is that AMD's power demo has 94W power delta between idle and load for Zen. So, yes, 95W for Zen is basically cutting it close to Typical Design Power, rather than Thermal Design Power.
There is no such thing as traditional SMT,whatever works for you(the CPU manufacturer) and allows two threads on one core is SMT.TheELf are you serious here or just trolling?
Zen is 8 cores with traditional SMT( aka HT in intel's case). There is no CMT in Zen, please just stop embarrassing yourself anymore.
So, uh, I didn't see any of the demos. Does Ryzen have 2x256-bit vector units instead of the 2x128-bit that was rumored?
No idea.. I gave up. It's only a month or so until we find out for sure anyways.anyone have any idea what TheELF is on about?
But is NOT the CMT we know... is an hybrid (a very well done) of that and SMT.There is no such thing as traditional SMT,whatever works for you(the CPU manufacturer) and allows two threads on one core is SMT.
(also less hardware overhead better IPC and less power...sound familiar? )
https://www.google.com/search?tbm=bks&hl=el&q=Advanced+Parallel+Processing+Technologies:+6th+International+Workshop,+APPT+2005
Advanced Parallel Processing Technologies: 6th International Workshop, APPT 2005
There is no such thing as traditional SMT,whatever works for you(the CPU manufacturer) and allows two threads on one core is SMT.
I never said it where CMT I said it was like CMT.But is NOT the CMT we know... is an hybrid (a very well done) of that and SMT.
No it's not like HT,in HT the "partitioning" happens by the threads themselves (it's not even partitioning every core just takes what it can)and the cores are build for speed.OK, but that doesn't change the fact the SMT implementation on Zen is very similar to HT and has nothing in common with CMT.
AMD defines TDP as max power draw. Also Lisa Su specifically said the CPU is still being tuned. Usually power saving and boost features are the last to be optimized (as they can introduce instability while other performance features are being worked on). Fun fact: I was talking to the guy who worked on the Pebble watch design, who says that before they did power optimization the watch could only run 45 minutes before the battery was drained. Once they were done tweaking all power saving features they got a full week worth of battery life out of it.Hint is that AMD's power demo has 94W power delta between idle and load for Zen. So, yes, 95W for Zen is basically cutting it close to Typical Design Power, rather than Thermal Design Power.
I never said it where CMT I said it was like CMT.
No it's not like HT,in HT the "partitioning" happens by the threads themselves (it's not even partitioning every core just takes what it can)and the cores are build for speed.
In amds version, senseMI will be trying to do the partitioning in the best way possible for the best performance based on the workload and the cores are build for throughput and not speed.
At least that's how I see it.
TDP is universally defined as Thermal Design Power, how many watts of heat a heatsink must dissipate.AMD defines TDP as max power draw. Also Lisa Su specifically said the CPU is still being tuned. Usually power saving and boost features are the last to be optimized. Fun fact: I was talking to the guy who worked on the Pebble watch design, who says that before they did power optimization the watch could only run 45 minutes before the battery was drained. Once they were done tweaking all power saving features they got a full week worth of battery life out of it.
Wrong. Intel and AMD do it differently. Anandtech explains it in this article:TDP is universally defined as Thermal Design Power, how many watts of heat a heatsink must dissipate.
Actual power consumption can be significantly higher than TDP. The keyword here is thermal.
I've read the Family 10h datasheets.Wrong. Intel and AMD do it differently. Anandtech explains it in this article:
http://www.anandtech.com/show/2807/2
I am not missing anything no one is talking about current transients here. We're all talking about simple power draw measurement during a long running benchmark.I've read the Family 10h datasheets.
Here's a better read:
http://www.intel.com/content/dam/doc/white-paper/resources-xeon-measuring-processor-power-paper.pdf
I think Johan meant well when he wrote that article, but you are missing the point here.
Both the intel whitepaper and AMD datasheet: "The maximum power a processor draws for a thermally significant period while running commercially useful software. The constraining conditions for TDP are specified in the notes in the thermal and power tables."
Intel: "It is possible for the processor to consume more than the TDP power for a short period of time that isn’t “thermally
significant"
AMD (lifted straight from the Family 10h datasheet): "The processor thermal solution should be designed to accommodate thermal design power (TDP) at Tcase Max. TDP is measured under the conditions of all cores operating at CPU COF, Tcase Max, and VDD at the voltage requested by the processor. TDP includes all power dissipated on-die from VDD, VDDNB, VDDIO, VLDT, VTT, and VDDA. TDP is not the maximum power of the processor."
I was clearly talking about HT, with hyperthreading in intel one thread runs normally as if on a normal core and the second one only uses the instructions left over by the first.What do you mean 'by the threads themselves"?
Well, I just showed you that intel and AMD define TDP the same way, no?I am not missing anything no one is talking about current transients here. We're all talking about simple power draw measurement during a long running benchmark.
Well, I just showed you that intel and AMD define TDP the same way, no?
Extremely heavy multi-threaded workloads can push CPUs way past defined TDP, here is Carrizo up 50% past its TDP in Prime95:
http://www.anandtech.com/show/10436/amd-carrizo-tested-generational-deep-dive-athlon-x4-845/23
I'm not saying it happens all the time, but it definitely happens.
To be honest, I had originally looked at the 860K number and neglected to do any math *shrug*It s within its 65W TDP, dunno from where you are extracting your 70%, I would venture to guess that it s surely from a lack of homework since you consider that a delta at the main is equal to the delta at the CPU level, given s AT plateform the correction due to intermediary circutries losses is 0.775, do the maths...
And no, of course the delta at main is not equal to the delta at the CPU level, but the delta at CPU level isn't measured. It is impossible to calculate the delta at CPU level based on the varying AC to DC efficiency loss of the power supply at differing loads, and SMPS AC-->DC efficiency is usually lower at low loads.
The 845's delta is still ~+25% over its specified TDP in Prime95 and considerably higher than 65w.
There is no such thing as traditional SMT,whatever works for you(the CPU manufacturer) and allows two threads on one core is SMT.
AMD defines TDP as max power draw. Also Lisa Su specifically said the CPU is still being tuned. Usually power saving and boost features are the last to be optimized (as they can introduce instability while other performance features are being worked on). Fun fact: I was talking to the guy who worked on the Pebble watch design, who says that before they did power optimization the watch could only run 45 minutes before the battery was drained. Once they were done tweaking all power saving features they got a full week worth of battery life out of it.
Yep. But if thats the case then what does that tell us.I somewhat agree with TheELF here, either way you put it if we put relative performance of a 8c/16t zen equal to a 8c/16t broadwell, then it goes to reason that for the given workload, if HT threads on the Zen platform pulled a larger utilization level than the equal HT onthe Intel platform, then Zen ST performance will be lower.
All structures fully available in ONE thread mode, this is a hint that 2 threads cant have twice the throughput of a single thread.